Memory Repair Optimized Redundancy Utilization
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Solution Overview
Problem
Memory dies with defective cells cannot be fully repaired using redundancy cells when the number of defective cells exceeds the number of redundancy word lines, leading to discarding of memory dies.
Innovation Solution
Implementing a redundancy fuse region with programmable read-only memory elements to logically replace defective primary word lines with replacement word lines and substitution memory cells to restore functionality, and using a sorting process to optimize the replacement of defective memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy word lines are used to replace defective primary word lines, then memory die yield is improved, but the number of repairable dies is limited by the total number of redundancy word lines
Solution Approach 1:
The patent segments the redundancy resource into two distinct types: redundancy word lines for replacing entire defective word lines, and substitution memory cells for replacing individual defective memory cells. This segmentation allows the system to handle different defect scenarios with appropriate repair mechanisms, thereby increasing overall repair capacity beyond what a single redundancy resource type could provide.
Solution Approach 2:
The patent adds a new dimension to the repair strategy by introducing substitution memory cells that can be individually activated to replace specific defective memory cells within or across word lines. This dimensional addition transforms the repair capability from a word-line-level operation to a cell-level operation, enabling repair of dies that exceed the redundancy word line capacity.
2Reliability
If all redundancy word lines are allocated to replace defective word lines, then word line defects are repaired, but substitution memory cells cannot be optimized for repairing remaining defective cells
Solution Approach 1:
The patent implements a preliminary sorting process that identifies and categorizes defective memory cells before repair allocation. This preliminary action enables the system to determine which defective cells can be repaired by substitution memory cells versus those requiring redundancy word line replacement, optimizing the allocation of repair resources before the actual repair process begins.
Solution Approach 2:
The patent changes the repair approach parameter from a uniform redundancy word line replacement strategy to a differentiated strategy that selects between redundancy word lines and substitution memory cells based on defect characteristics. This parameter change enables optimized repair efficiency by matching the appropriate repair mechanism to each defect type and location.
3Reliability
If memory dies with high bit error rates are repaired using available redundancy, then near 100% yield is achieved, but complex sorting and allocation processes are required
Solution Approach 1:
The patent implements a self-service repair management system where the sorting and allocation logic is automatically performed by the memory device itself during initialization. The device autonomously identifies defective cells, sorts them by repairability, and allocates appropriate repair resources without external intervention, thereby managing the complexity internally while maintaining high yield.
Solution Approach 2:
The patent incorporates feedback mechanisms where the results of preliminary sorting and defect analysis are used to dynamically adjust the repair allocation strategy. The system uses feedback from defect detection to optimize the use of redundancy resources, ensuring that substitution memory cells and redundancy word lines are allocated to the most appropriate defects, thereby achieving high yield while managing complexity through intelligent control.
Data Source
AI summary
A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.