Memory Repair Resource Allocation via Priority Selection Circuit

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Solution Overview

Problem

Existing memory technologies face inefficiencies in yield due to the abandonment of memories with a small number of defective cells, and there is a need for effective resource allocation and management for post-package repair.

Innovation Solution

A memory system that includes register circuits for storing failure addresses, resource latch circuits for indicating availability, and a priority selection circuit for efficiently allocating and managing repair resources, allowing for soft repair operations and resource management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a memory with a small number of defective cells is abandoned as a defective product, then manufacturing quality control is simplified, but yield is reduced

Engineering Contradiction:
Improvequality controlVSAvoidyield
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-configuring multiple register circuits (first to Nth register circuits) and their corresponding resource latch circuits before the actual repair operation. This allows the memory system to proactively prepare repair resources and quickly respond to defective cells during operation, rather than abandoning memories with minor defects. The priority selection circuit is also pre-established to automatically manage resource allocation when defects are detected.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If multiple register circuits are provided for storing failure addresses, then repair resource availability is improved, but device complexity increases

Engineering Contradiction:
Improverepair resource availabilityVSAvoidcircuit structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements feedback through resource latch circuits that continuously monitor and indicate the availability status of each register circuit. When a register circuit is occupied by a failure address, its corresponding resource latch circuit reflects this state, providing real-time feedback to the priority selection circuit. This feedback mechanism enables automatic resource management without increasing operational complexity, as the system self-regulates based on the latch circuit signals.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The resource latch circuits serve as intermediaries between the register circuits and the priority selection circuit. Instead of directly managing the complex states of multiple register circuits, the priority selection circuit simply responds to the simplified availability signals from the latch circuits. This intermediary layer abstracts the complexity, making the resource management system more manageable while maintaining adaptability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If a priority selection circuit is implemented to allocate repair resources, then resource management efficiency is improved, but device complexity increases

Engineering Contradiction:
Improveresource management efficiencyVSAvoidcontrol circuit
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies local quality by giving different priority levels to different register circuits based on their resource availability status. The priority selection circuit selectively activates specific register circuits depending on the current state of resource latch circuits, rather than treating all register circuits equally. This localized priority assignment optimizes resource management efficiency by directing repair operations to the most appropriate available resources without requiring a globally complex control structure.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250095769A1Memory and operation method thereof
Publication Date: 2025.03.20 SK HYNIX INC
  • US20250095769A1 patent drawing
  • US20250095769A1 patent drawing
  • US20250095769A1 patent drawing

AI summary

A memory includes: first to Nth register circuits each suitable for receiving and storing a failure address transferred from a memory controller when a corresponding selection signal of first to Nth selection signals is activated, where N is an integer equal to or greater than 2; first to Nth resource latch circuits suitable for storing first to Nth resource signals indicating availability of the first to Nth register circuits, respectively; and a priority selection circuit suitable for activating, when two or more of the first to Nth resource signals are activated, one of selection signals respectively corresponding to the activated resource signals among the first to Nth selection signals.