Memory Repair Circuit for Row Hammer-Aware Redundant Row Use
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Solution Overview
Problem
The utilization rate of the redundant memory area in DRAM is reduced due to the row hammer problem, which prevents the memory cell closest to the normal memory area from being used, leading to resource wastage and reduced efficiency.
Innovation Solution
A repair circuit is introduced, comprising a first control circuit and a repair determination module, which processes signals from the row address to determine whether to use the target repair unit adjacent to the normal memory area for repairing abnormal memory cells, thereby improving the utilization of redundant memory area resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory cell closest to the normal memory area in the redundant memory area is excluded from use due to row hammer problem, then the reliability of the memory system is improved, but the utilization rate of the redundant memory area deteriorates
Solution Approach 1:
The patent implements dynamic control of the target repair unit by using a control circuit that monitors row address signals and dynamically enables or disables the target repair unit based on whether the current access pattern poses a row hammer risk. This allows the system to adaptively switch between safety mode (disabling target repair unit) and efficiency mode (enabling target repair unit), resolving the contradiction between reliability and utilization rate
Solution Approach 2:
The system changes the operational state parameter of the target repair unit from permanently disabled to conditionally enabled based on row address analysis. By modifying this parameter dynamically according to access patterns, the system achieves both high reliability (when disabled) and high utilization (when enabled), resolving the technical contradiction
2Productivity
If the target repair unit is enabled to repair abnormal memory cells, then the utilization rate of redundant memory area is improved, but the risk of row hammer interference increases
Solution Approach 1:
The patent introduces a control circuit as an intermediary between the row address input and the target repair unit. This intermediary analyzes the row address signals and mediates the activation of the target repair unit, allowing the system to exploit the target repair unit for improving utilization while filtering out dangerous access patterns that could cause row hammer interference
Solution Approach 2:
The system implements feedback control by continuously monitoring row address signals and using this information to control the activation of the target repair unit. The control circuit receives feedback from the address decoding process and adjusts the operational state of the target repair unit accordingly, enabling the system to achieve high utilization while maintaining protection against row hammer attacks
Data Source
AI summary
The repair circuit is disposed in a memory including a normal memory area and a redundant memory area including a target repair unit immediately adjacent to the normal memory area, and the repair circuit being configured to control the target repair unit to repair an abnormal memory cell in the normal memory area. The repair circuit includes: a first control circuit, configured to receive signals at a target number of bits from low to high in a row address, process the received signals to obtain a control result, and output the control result, where the target number is associated with a number of Word Lines in the target repair unit; and a repair determination circuitry, connected to an output terminal of the first control circuit, and configured to receive the control result and output, in combination with the control result, a repair signal indicating whether to perform a repair operation.