Semiconductor Memory Repair Signal Timing Compensation
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Solution Overview
Problem
Conventional semiconductor memory apparatuses face challenges in generating a repair detecting signal at a predetermined timing due to varying signal transfer delays for different addresses, leading to inconsistent and unreliable data access.
Innovation Solution
The semiconductor memory apparatus incorporates a circuit with adjustable fuse widths and a signal accelerating unit to maintain consistent transition times for repair detecting signals across different addresses, ensuring reliable data access by compensating for signal transfer delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different address signal paths are used in the semiconductor memory apparatus, then the apparatus can handle multiple addresses, but the signal transfer delays vary for different addresses causing inconsistent repair detecting signal timing
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the delay characteristics of each address signal path using fuses with different widths before operation. The fuse widths are predetermined during manufacturing to compensate for path-specific delays, ensuring that all address signals arrive at the repair detecting circuit simultaneously without requiring real-time adjustment during device operation.
Solution Approach 2:
The patent changes the physical parameter of fuse width to control signal delay characteristics. By varying the fuse width across different address paths, the resistance and consequently the signal propagation delay are adjusted. This parameter modification enables synchronization of arrival times for repair detecting signals across all address paths while maintaining the ability to handle multiple addresses.
2Reliability
If fuse widths are adjusted to compensate for signal transfer delays, then the repair detecting signal timing becomes consistent, but the circuit design becomes more complex
Solution Approach 1:
The patent applies local quality by making each address signal path have unique fuse width characteristics tailored to its specific delay requirements. Instead of using a uniform delay compensation mechanism for all paths, each path is locally optimized with fuses of appropriate widths, allowing simple individual path adjustment rather than a complex global synchronization system.
Solution Approach 2:
The fuse structure serves as an intermediary element between the address input and the repair detecting circuit. By introducing this passive delay compensation component in series with each address path, the complex timing synchronization problem is transformed into a simple resistance-based delay adjustment, reducing the overall circuit design complexity while achieving reliable timing consistency.
Data Source
AI summary
A first input unit, coupled to a repair checking node through a first fuse, is for inverting a logic level of the repair checking node in response to a first address. A second input unit, coupled to the repair checking node through a two or more second fuses, is for inverting a logic level of the repair checking node in response to a second address. The number of the second fuses corresponds to a delay time between a transfer path of the first address and a transfer path of the second address. A repair detecting signal generating unit is for generating a repair detecting signal in response to the logic level of the repair checking node. Other embodiments are also described.