Semiconductor Memory Repair via Standard Access Protocol
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Solution Overview
Problem
Semiconductor memory devices often require repair operations after packaging, but existing methods are limited in efficiently performing these repairs using standard memory access protocols.
Innovation Solution
The method involves a semiconductor memory device with a fuse array for storing repair addresses, which can latch additional repair addresses during a repair operation mode, receive a repair entry control code, perform a rupture operation based on this code, and exit the repair mode upon a precharge command, allowing for repair operations to be conducted using normal memory access protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repair operations are performed after packaging using existing methods, then device functionality can be restored, but the repair process requires complex specialized protocols and procedures
Solution Approach 1:
The patent makes the memory device's interface universal by enabling it to accept repair commands through standard memory access protocols that external devices already use, rather than requiring specialized repair protocols. The mode register set acts as a universal interface layer that translates standard access commands into repair operations, allowing the same interface to serve both normal memory access and repair functions.
Solution Approach 2:
The memory device performs repair operations autonomously using its own internal resources. The fuse array, rupture operation unit, and mode register set are all internal components that enable the device to self-diagnose and self-repair without requiring external specialized equipment or complex external control protocols.
2Adaptability or versatility
If additional repair addresses are latched during repair operation mode, then more repair locations can be addressed, but the operation mode requires specific command sequences
Solution Approach 1:
The mode register set serves multiple functions: it controls entry into repair operation mode, manages latching of repair addresses, and controls exit from repair mode. By using a single multi-functional register to manage the entire repair process, the patent avoids requiring separate control mechanisms for each function, thereby simplifying the overall command sequence while maintaining versatility.
Solution Approach 2:
The repair address is latched in advance during the repair operation mode before the actual rupture operation is executed. This preliminary latching action prepares the device for the subsequent rupture operation, allowing the repair address to be ready and stored in the appropriate register before the fuse rupture occurs, thereby streamlining the overall repair sequence.
3Manufacturing precision
If rupture operation is performed based on repair entry control code, then precise control over repair process is achieved, but the process requires sequential command execution
Solution Approach 1:
The mode register set is configured in advance to enter repair operation mode before the actual rupture operation begins. This preliminary configuration includes setting the appropriate control bits and preparing the fuse array for rupture, so that when the rupture command is finally issued, all preparatory conditions are already met and the operation can proceed immediately without delays.
Solution Approach 2:
The repair entry control code provides feedback control for the rupture operation. The control code value determines whether the rupture operation should be executed, allowing the system to verify conditions and make decisions based on the current state before proceeding with the irreversible fuse rupture, thereby ensuring precise control while maintaining efficient execution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables effective repair operations on semiconductor memory devices post-packaging through a standardized memory access protocol, ensuring reliable device functionality even after mounting on electronic devices.
Implementation Method 1
An electrical resistance value of the fuse is changed through change of an electrical characteristic of the fuse by a laser beam or an electrical stress.
Implementation Method 2
An electrical resistance value of the fuse is changed through change of an electrical characteristic of the fuse by a laser beam or an electrical stress.
Implementation Method 3
performing a rupture operation of the repair address, which is latched, on the fuse array in response to a second column command signal, wherein the rupture operation is determined based on a value of a repair entry control code
Data Source
AI summary
An operation method of a semiconductor memory device including a fuse array for storing one or more repair addresses includes latching additionally a repair address having an address value, which is not stored in the fuse array in response to an active command signal during a repair operation mode, receiving a repair entry control code from an external device in response to a first column command signal during the repair operation mode, performing a rupture operation of the repair address, which is latched, in response to a second column command signal, wherein the rupture operation is determined based on a value of a repair entry control code, and performing exit of the repair operation mode in response to a precharge command signal, which is provided after the second column command signal.