Memory Repair Circuit with Test Controller for In-Field Self-Repair
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Solution Overview
Problem
Integrated circuits face challenges in efficiently managing multiple memory in-field self-repair options, balancing IC footprint size, memory test efficiency, and repair flexibility, especially with increasing memory blocks in modern system-on-a-chip products.
Innovation Solution
A system-on-a-chip (SoC) with a memory repair circuit that includes a test controller to select between error mask and incremental repair circuits for in-field self-repair, providing local pass/fail determination, ECC-aware regionalization, and error masking, along with shadow fuse registers for cumulative repair codes and error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple repair circuits are provided for in-field self-repair, then repair flexibility and reliability are improved, but device complexity increases
Solution Approach 1:
The memory repair circuit is designed to perform multiple repair functions through a unified architecture that supports both error mask repair and incremental repair modes. The test controller can select between different repair methods based on the error type and available resources, allowing a single circuit to handle various repair scenarios without requiring separate dedicated circuits for each repair method.
Solution Approach 2:
The repair circuit incorporates dynamic selection capability where the test controller adapts its behavior based on real-time conditions. The system can switch between error mask repair and incremental repair modes depending on the number of errors detected, the type of memory block, and available redundant resources. This dynamic adaptation allows the circuit to optimize its operation without requiring multiple static repair paths.
2Adaptability or versatility
If ECC and incremental repair methods are both available, then repair flexibility is improved, but IC footprint size increases
Solution Approach 1:
The memory repair circuit is designed to perform multiple repair functions through a unified architecture that supports both error mask repair and incremental repair modes. The test controller can select between different repair methods based on the error type and available resources, allowing a single circuit to handle various repair scenarios without requiring separate dedicated circuits for each repair method.
Solution Approach 2:
The patent combines the error mask circuit and incremental repair circuit into a single integrated memory repair circuit structure. By merging these functions into one circuit block with shared components, the design achieves both repair methods without requiring separate dedicated circuits, thereby reducing the overall IC footprint while maintaining repair flexibility.
3Adaptability or versatility
If more memory blocks are included in the IC, then functionality is improved, but memory test and repair efficiency decreases
Solution Approach 1:
The memory block is divided into multiple testable units with individual pass/fail determination capability. The test controller can independently test and repair each segment, allowing parallel testing operations. This segmentation enables efficient testing of large memory blocks by processing them in manageable units simultaneously, improving overall test productivity.
Solution Approach 2:
The system performs partial repairs by addressing only the defective segments rather than the entire memory block. The test controller identifies specific failing units and applies repair only to those segments, leaving functional areas unchanged. This partial action approach reduces test time and repair overhead compared to comprehensive retesting of the entire memory block.
Data Source
AI summary
A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.