Memory Device Secondary Repair Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As manufacturing processes for memory devices like DRAM and flash memory reduce in scale, additional failed blocks can occur after primary repairs, necessitating secondary repairs and verification during the package stage, which is not effectively addressed by existing technologies.
Innovation Solution
A memory device and system that includes a memory cell array with normal and redundant regions, a control circuit with a test mode register and mapping table, allowing for secondary repairs and verification of replacing failed blocks with redundant blocks during the package stage by writing specific logic values and updating the mapping table based on data read from the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manufacturing process scale is reduced to increase production capacity, then productivity is improved, but the number of failed memory cells increases significantly
Solution Approach 1:
The patent performs preliminary repair actions during wafer fabrication before cutting and packaging. Failed blocks are identified and replaced with redundant blocks during electrical die sorting (EDS) test at the wafer stage, preventing defective units from proceeding to later stages where repair becomes more difficult or impossible.
Solution Approach 2:
The memory device includes a redundant region with spare blocks prepared in advance to compensate for potential failures. When failures occur during or after manufacturing, these pre-positioned redundant blocks serve as backup resources to replace defective blocks, cushioning the impact of manufacturing defects on overall yield.
2Reliability
If primary repair is performed during wafer stage to replace failed blocks with redundant blocks, then reliability is improved, but additional failed blocks may still occur after packaging requiring secondary repair
Solution Approach 1:
The control circuit performs preliminary repair operations during wafer fabrication by identifying failed blocks and mapping them to redundant blocks during EDS testing. This preliminary repair catches most defects before packaging, reducing the need for complex post-package repair operations.
Solution Approach 2:
The control circuit includes self-diagnostic and self-repair capabilities that automatically detect failed blocks and perform replacement operations without external intervention. The circuit can identify defects, select appropriate redundant blocks, and execute repair operations autonomously during testing phases.
3Reliability
If secondary repair is performed in package stage for additional failed blocks, then reliability is improved, but verification of secondary repair becomes necessary increasing complexity
Solution Approach 1:
The control circuit incorporates feedback mechanisms that automatically verify repair operations by reading back data from replaced blocks and comparing against expected values. This feedback loop confirms successful repair without requiring complex external verification equipment or procedures.
Solution Approach 2:
The control circuit performs self-verification of repair operations by automatically testing the functionality of replaced blocks and confirming proper operation. This self-service verification capability eliminates the need for separate, complex verification processes.
4Adaptability or versatility
If redundant region is included in memory device to enable block replacement, then adaptability for repair is improved, but device area increases
Solution Approach 1:
The memory device structure divides the array into normal regions for data storage and a separate redundant region for backup blocks. This local differentiation allows the majority of the device area to be dedicated to high-density data storage while a smaller portion is allocated to redundancy, optimizing the balance between storage capacity and repair capability.
Solution Approach 2:
The redundant blocks in the redundant region serve multiple functions: they can replace failed blocks during wafer-stage repair, provide backup for post-package failures, and enable various repair strategies. This multi-functionality maximizes the utility of the redundant region, justifying its area allocation.
Data Source
AI summary
A memory device that includes a memory cell array and control circuit in which the memory cell array includes a normal region including a first failed block and a redundant region including a first redundant block replacing the first failed block. The control circuit includes a mapping table storing replacement information. The control circuit refers to the mapping table for accessing the first redundant block. When testing the memory device, the control circuit writes “1” in the normal region and the first redundant block, writes “0” in the redundant region except the first redundant block, adds the replacement information regarding a second failed block and second redundant block in the redundant region to the mapping table and verifies the result of replacing the second failed block with the second redundant block based on entire data read from the memory cell array with respect to entire range assigned to the address signal.