Memory Self-Repair Verification Circuit
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Solution Overview
Problem
Current memory systems lack a reliable method to verify whether a self-repair operation, such as the mPPR sequence, has successfully replaced a failed row address with a redundant one, leading to potential incorrect data retrieval and increased error processing overhead.
Innovation Solution
Incorporating a verification circuit that performs a series of access operations on the repaired memory row to confirm the successful replacement of a failed row with a redundant row by writing data to the redundant row and attempting to read it from the original failed row address, using an error flag to indicate the success or failure of the repair operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a self-repair operation is performed to replace a failed row address with a redundant one, then the reliability of the memory system is improved, but there is no verification method to confirm successful repair leading to potential incorrect data retrieval
Solution Approach 1:
The patent implements a verification circuit that performs feedback operations by writing test data to the repaired memory row and reading it back to verify the repair was successful. This closed-loop feedback mechanism confirms whether the redundant row is functioning correctly before normal operations resume, ensuring measurement precision of repair success.
Solution Approach 2:
The memory system performs self-verification through integrated test circuitry that automatically tests the repaired row without external intervention. The system writes test patterns, reads them back, and determines repair success autonomously, improving both reliability and verification accuracy simultaneously.
2Measurement precision
If verification operations are added to confirm successful repair, then the measurement precision of repair status is improved, but the error processing overhead increases
Solution Approach 1:
The patent performs verification operations immediately after the repair operation in a predetermined sequence, rather than waiting for errors to manifest during normal operation. This preliminary verification prevents future errors and reduces processing overhead by catching issues before they affect system performance.
Solution Approach 2:
The verification circuit is integrated into the existing memory control logic, merging the verification function with the repair operation workflow. This consolidation allows verification to occur within the same operational framework without requiring separate processing cycles, thereby improving measurement precision while minimizing additional time overhead.
3Reliability
If a verification circuit is implemented to test repaired rows, then the reliability of data retrieval is improved, but the device complexity increases
Solution Approach 1:
The verification circuit utilizes existing memory control components and data paths for multiple purposes: normal read/write operations, repair operations, and verification operations. By making these components multi-functional, the patent improves data retrieval reliability through verification without proportionally increasing device complexity.
Solution Approach 2:
The patent introduces an intermediary verification step that acts as a mediator between the repair operation and normal data retrieval. This intermediary layer uses simple write-read-compare logic to verify repair success, improving reliability while maintaining relatively low complexity compared to more sophisticated verification schemes.
Data Source
AI summary
Methods, systems, and devices for self-repair verification are described. A memory system may receive, at a memory device, a command to initiate a repair operation. The memory system may perform the repair operation by replacing a first row of memory cells of the memory device with a second row of memory cells of the memory device. The memory system may write first data to the second row of memory cells, and read second data from the second row of memory cells, based on a stored indication associated with the replacement of rows. The memory device may output an error flag with a first value based at least in part on reading the second data, and the first value of the error flag may indicate that the repair operation was successfully performed based at least in part on the second data matching the first data.