Memory Subsystem Repeater Architecture for Narrow Bandwidth Channel Extension
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional memory systems face limitations in scaling processor performance due to the tradeoff between increasing memory bandwidth and capacity, as multidrop memory channels degrade with additional memory devices, leading to bandwidth bottlenecks and impractical increases in signal lines and device size.
Innovation Solution
Implementing a repeater architecture that converts multidrop connections to point-to-point channels, allowing for higher data rates by sharing bandwidth between primary and secondary memory modules, with a buffer that repeats the channel to extend connectivity without increasing signal lines, enabling efficient data transfer between memory modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multidrop memory channels are used to connect multiple memory devices to the processor, then memory capacity can be increased, but the loading on the memory channel degrades the communication over the bus and bandwidth is reduced
Solution Approach 1:
The memory channel is segmented into multiple independent point-to-point channels, each connecting the processor to a specific memory module. This segmentation eliminates the shared bus architecture of multidrop channels, allowing each channel to operate independently at full bandwidth without degradation from other memory devices on the same channel.
Solution Approach 2:
The patent transitions from a single-dimension shared bus architecture to a multi-dimensional point-to-point topology where multiple independent channels operate in parallel. This dimensional change allows simultaneous high-bandwidth communication with multiple memory modules without the capacitive loading problems of traditional multidrop channels.
2Quantity of substance
If the number of memory devices on a multidrop channel is increased, then memory capacity increases, but the number of signal lines and device size must increase impractically
Solution Approach 1:
The system segments the memory subsystem into multiple independent point-to-point channels, each with its own dedicated signal lines. This allows memory capacity to be increased by adding more channels rather than adding more devices to existing channels, keeping the signal line count per channel manageable and avoiding the exponential growth of complexity associated with multidrop architectures.
3Stability of the object's composition
If traditional multidrop memory channels are used, then existing architecture is maintained, but data rate limit is reached with two memory modules installed
Solution Approach 1:
The patent implements a dynamic memory channel architecture that can adapt between different configurations. The point-to-point channels are designed to be scalable and can be configured to support various numbers of memory modules while maintaining high data rates. This dynamic approach allows the system to exceed the data rate limits of traditional multidrop channels while maintaining architectural flexibility and compatibility.
Data Source
AI summary
A system with memory includes a repeater architecture where the memory connects to a host with one bandwidth, and a repeater extends a channel with a lower bandwidth. A memory circuit includes a first group of memory devices coupled point-to-point to a host device via a first group of read signal lines. The memory circuit includes a second group of memory devices coupled point-to-point to the first group of memory devices second group of read signal lines to extend the memory channel to the second group of memory devices. The second group of read signal lines has fewer read signal lines than the first group. The memory circuit includes a repeater to share read bandwidth between the first and second groups of memory devices, with up to a portion of the bandwidth for reads to the second group of memory devices, and at least an amount equal to the bandwidth less the portion for reads to the first group of memory devices. The repeater or buffer may accumulate data read from the second group of memory devices or a second memory module and burst the accumulated data to the host device with the first bandwidth.