Semiconductor Memory Device Replica Circuit Timing Quantization
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in accurately generating activation timing for sense amplifiers due to delays in replica circuits, which can lead to misreading and fail to reflect changes in memory cell characteristics, especially under varying temperature conditions.
Innovation Solution
A semiconductor memory device incorporating a replica circuit with a timing generating circuit that quantizes replica delay time to generate an activation timing for the sense amplifier, ensuring accurate simulation of memory cell operations and adapting to changes in memory cell characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the sense amplifier is activated fast, then the operating period is shortened, but data misreading occurs due to insufficient signal level
Solution Approach 1:
The replica circuit performs preliminary simulation of the memory cell array's read operation to predict the signal level timing. The replica bit line is pre-charged and then discharged through the replica memory cell to generate a timing signal that indicates when the actual bit line signal will be sufficient for accurate sensing.
2Measurement precision
If a replica circuit is used to generate activation timing, then the timing is more accurate, but delay times from intermediate circuits cause simulation inaccuracy
Solution Approach 1:
The invention extracts only the essential timing-generating function from the replica circuit by directly utilizing the replica bit line's voltage transition signal, eliminating the need for intermediate delay circuits that would add unwanted time losses and reduce timing accuracy.
3Device complexity
If the replica circuit structure is simplified, then the device complexity is reduced, but the ability to reflect memory cell characteristic changes is compromised
Solution Approach 1:
The replica circuit is designed with the same homogeneous structure as the memory cell array, using identical memory cells, word lines, and bit lines. This ensures that the replica circuit naturally reflects memory cell characteristic changes under varying conditions without requiring additional complexity.
Data Source
AI summary
A semiconductor memory device comprises a plurality of word lines, a plurality of bit lines intersecting the word lines, a memory cell array having a plurality of memory cell each provided at an intersection of the word line and the bit line, a plurality of sense amplifier each of which detects and amplifies a signal level of the bit line, a replica word line, a replica bit line intersecting the replica word line, a replica memory cell provided at each intersection of the replica word line and the replica bit line, a replica circuit which simulates reading out of the memory cell, and a timing generating circuit which quantizes a replica delay time that is a time until the replica bit line changes from a reference timing, and which generates an activation timing for the sense amplifier based on a quantization result.