Memory Access Request Aggregation for Bandwidth Utilization
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Solution Overview
Problem
The existing caching techniques in computer processors are inefficient for handling memory access requests with poor data locality, leading to high latency and bandwidth wastage, especially when multiple cores send concurrent memory access operations, causing congestion in the memory controller and delayed processing.
Innovation Solution
Combining multiple memory access requests with low bandwidth utilization into a single new request with high bandwidth utilization, using a code bit vector and first code bit identifier to ensure accurate execution by the memory controller, thereby reducing the number of requests and improving processing timeliness and bandwidth utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple memory access requests are sent separately to the memory controller, then each request can be processed individually, but the bandwidth utilization is low and the memory controller becomes congested
Solution Approach 1:
The patent combines multiple memory access requests into a single unified request before sending to the memory controller. The processing apparatus aggregates multiple requests that access different memory addresses within the same memory bank, merges them into one request containing a bitmap indicating which addresses need access, and sends this consolidated request to the memory controller. This reduces the number of requests, improves bandwidth utilization, and prevents controller congestion while maintaining accurate processing of each individual address through the bitmap mechanism.
2Reliability
If the memory controller processes requests sequentially, then processing accuracy is maintained, but the processing timeliness deteriorates under high concurrency
Solution Approach 1:
By merging multiple memory access requests into a single consolidated request with a bitmap, the patent enables the memory controller to process multiple addresses in one operation rather than sequentially. This significantly reduces processing time under high concurrency conditions while maintaining accuracy through the bitmap that precisely specifies which memory addresses require access within the unified request.
3Measurement precision
If data is accessed with fine granularity, then processing precision is improved, but the number of memory access requests increases
Solution Approach 1:
The patent resolves this contradiction by combining multiple fine-grained memory access requests into a single unified request. The unified request maintains fine-grained access precision through a bitmap that specifies exactly which memory addresses need to be accessed, while reducing the number of requests sent to the memory controller. This approach preserves access precision without increasing request quantity, as multiple precise requests are merged into one equally precise consolidated request.
Data Source
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AI summary
The present invention provides a memory access processing method and apparatus, and a system, where the method includes: receiving a memory access request sent by a processor; combining multiple memory access requests received within a preset time period to form a new memory access request, where the new memory access request includes a code bit vector consisting of code bits corresponding to memory addresses, a base address of the memory addresses accessed by the memory access requests that are combined, a memory access granularity and a memory access request type; and a first code bit identifier indicating there is a memory access operation is configured for the code bits that are in the code bit vector and corresponding to the memory addresses accessed by the memory access requests that are combined; and sending the new memory access request to a memory controller, so that the memory controller executes a memory access operation on a memory address corresponding to the first code bit identifier. According to the present invention, multiple memory access requests sent by the processor can be combined into a memory access request and sent to the memory controller in a unified manner, so as to execute a memory access operation, which effectively improves memory bandwidth utilization.