Memory Request Aggregation for Parallel Execution Synchronization

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Solution Overview

Problem

Parallel processing systems face inefficiencies due to multiple execution units independently requesting memory data, leading to excessive bandwidth consumption and synchronization mechanisms that impact timing and power usage.

Innovation Solution

Implementing request aggregation circuits that combine memory requests from multiple execution units into a single representative request, synchronizing execution without explicit barriers, and managing data distribution efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If multiple execution units independently request memory data, then each unit can operate autonomously and concurrently, but bandwidth consumption increases excessively

Engineering Contradiction:
Improveconcurrent operation speedVSAvoidbandwidth consumption
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent combines multiple independent memory requests from different execution units into a single aggregated memory request. The memory management unit intercepts requests from multiple execution units and merges them into one consolidated request to the memory subsystem, reducing bandwidth consumption while maintaining concurrent processing capability.

Inventive Principle:
Principle #5Merging (Combining)

2Stability of the object's composition

If explicit synchronization barriers are implemented, then execution units can be synchronized, but timing is impacted and power consumption increases

Engineering Contradiction:
ImprovesynchronizationVSAvoidpower consumption
Core Design Contradiction:
Stability of the object's compositionVSUse of energy by stationary object

Solution Approach 1:

The system achieves synchronization automatically through the request aggregation mechanism without requiring explicit synchronization barriers from software. The memory management unit naturally synchronizes execution units by aggregating their requests, eliminating the need for additional power-consuming synchronization instructions.

Inventive Principle:
Principle #25Self-service

3Stability of the object's composition

If explicit synchronization barriers are implemented, then execution units can be synchronized, but system timing is slowed down

Engineering Contradiction:
ImprovesynchronizationVSAvoidexecution timing
Core Design Contradiction:
Stability of the object's compositionVSLoss of time

Solution Approach 1:

Synchronization is achieved automatically through the request aggregation mechanism without requiring explicit synchronization barriers from software. The memory management unit naturally synchronizes execution units by aggregating their requests, eliminating the need for additional power-consuming synchronization instructions.

Inventive Principle:
Principle #25Self-service

4Adaptability or versatility

If multiple independent memory requests are sent, then each execution unit can access memory independently, but the number of memory transactions increases

Engineering Contradiction:
Improveindependent access capabilityVSAvoidmemory transaction efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent combines multiple independent memory requests from different execution units into a single aggregated memory request. The memory management unit intercepts requests from multiple execution units and merges them into one consolidated request to the memory subsystem, reducing bandwidth consumption while maintaining concurrent processing capability.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20260079713A1Parallel processing memory traffic aggregation
Publication Date: 2026.03.19 ATI TECHNOLOGIES ULC
  • US20260079713A1 patent drawing
  • US20260079713A1 patent drawing
  • US20260079713A1 patent drawing

AI summary

A processor includes a plurality of execution units that perform respective portions of a parallel execution. As part of the parallel execution, each execution unit requests respective execution data via a respective memory request. A request aggregation circuit combines received memory requests from the execution units. Combining the requests includes identifying the memory requests as corresponding to the same execution data, sending a single representative memory request for the execution data, receiving a single instance of the execution data, and providing the respective execution data to each requesting execution unit.