Processor Memory Request Combination Indication

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Solution Overview

Problem

Current processor architectures underutilize system bandwidth due to inefficient memory request handling, leading to performance bottlenecks and increased power consumption, especially when handling multiple memory requests of varying sizes.

Innovation Solution

Implementing a memory request combination indication mechanism in processor cores that sends a non-binding sequential-access-may-follow hint to a transaction bundler, allowing for speculative combination of memory requests based on virtual address analysis, thereby improving bandwidth utilization and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory requests are handled individually without combination, then processing simplicity is maintained, but system bandwidth utilization is underutilized and power consumption increases

Engineering Contradiction:

Improvebandwidth utilizationVSAvoidmemory request handling complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by having the processor core send a combination indication hint before the memory requests are fully processed. This hint signals to the transaction bundler that sequential accesses may follow, allowing the bundler to proactively prepare for and combine multiple requests into a single transaction, thereby improving bandwidth utilization before the actual memory operations occur.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces a transaction bundler as an intermediary component between the processor core and the memory system. This bundler receives memory requests from multiple processor cores, combines compatible requests into single transactions, and manages the complexity of request combination logic centrally, thereby improving overall system bandwidth without significantly increasing the complexity of individual processor cores.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If memory requests are combined speculatively based on virtual address analysis, then bandwidth utilization improves, but processing time and complexity increase

Engineering Contradiction:

Improvetransaction efficiencyVSAvoidrequest processing time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent applies partial action by implementing speculative combination only for memory requests that exhibit patterns indicating potential combinability (such as sequential virtual addresses). Not all memory requests undergo speculative combination - only those that match the predicted pattern. This selective approach improves transaction efficiency for eligible requests while avoiding the time penalty for requests that don't benefit from combination.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The processor core performs preliminary virtual address analysis to generate combination hints before memory requests are fully issued. This preliminary analysis allows the transaction bundler to make combination decisions faster, reducing the overall processing time compared to waiting for all request details to be fully processed before determining combinability.

Inventive Principle:

Principle #10Preliminary action

3Use of energy by moving object

If multiple memory requests of varying sizes are handled separately, then request processing is straightforward, but power consumption increases due to multiple transactions

Engineering Contradiction:

Improvepower consumptionVSAvoidtransaction bundling mechanism

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent directly applies merging by combining multiple memory requests of varying sizes into a single unified transaction when they exhibit combinable patterns. The transaction bundler aggregates the data payloads from multiple requests and issues them as one consolidated memory transaction, thereby reducing the total number of transactions and associated power consumption while managing the complexity of handling variable-sized requests through centralized bundling logic.

Inventive Principle:

Principle #5Merging (Combining)

4Productivity

If a non-binding sequential-access-may-follow hint is sent to the transaction bundler, then bandwidth utilization improves through speculative combination, but the risk of incorrect speculation increases

Engineering Contradiction:

Improvebandwidth utilizationVSAvoidspeculation accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies partial action by making the combination indication non-binding rather than mandatory. The transaction bundler uses the hint to speculate on potential combinations, but retains the ability to issue separate transactions if the speculation proves incorrect or if other constraints prevent combination. This partial application of speculative combining improves bandwidth utilization for correct predictions while limiting reliability risks by allowing fallback to conservative separate transactions when speculation fails.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS20240020012A1Memory Request Combination Indication

Publication Date: 2024.01.18 SIFIVE INC

AI summary

A processor core may include circuitry that fetches a first instruction followed by a second instruction. The first instruction may be configured to cause a first memory request, and the second instruction may be configured to cause a second memory request. The circuitry may determine that the first memory request is a candidate for combination with the second memory request. Responsive to the determination, the circuitry may send an indication, from the processor core via a bus, that the first memory request is a candidate for combination.