Memory Request Converter for TLB Miss Latency and Bus Scheduling
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Solution Overview
Problem
Existing memory access systems experience high latency due to cache misses and translation lookaside buffer (TLB) misses, leading to inefficient utilization of buses and increased power consumption.
Innovation Solution
A converter module is introduced between the cache and main memory to handle memory requests, assigning transaction identifiers, tracking request status, and prioritizing MMU requests, enabling out-of-order issuance and address translation, thereby reducing latency and improving bus efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If memory requests are handled in strict order with traditional cache-TLB-memory access, then address translation accuracy is maintained, but access latency increases significantly
Solution Approach 1:
The system performs address translation requests to the TLB in advance before the actual memory access is needed. When a cache miss occurs, the converter module proactively initiates TLB translation requests, allowing the translation to be completed or at least progressed before the memory access deadline, thereby reducing overall latency while maintaining accuracy.
Solution Approach 2:
A converter module is introduced as an intermediary between the cache and main memory. This converter module manages the interaction between cache misses and TLB translations, coordinating the timing and ordering of operations. It buffers and reorders requests, allowing TLB translations to proceed without blocking critical memory accesses, thus resolving the latency-accuracy tradeoff.
2Reliability
If the system waits for TLB translation completion before issuing memory requests, then translation correctness is ensured, but bus utilization efficiency decreases
Solution Approach 1:
The system dynamically adjusts the ordering and timing of memory requests based on TLB translation status. The converter module monitors translation progress and adaptively reorders requests, issuing memory requests as soon as their translations are ready rather than waiting for all translations to complete. This dynamic approach ensures correctness while maximizing bus utilization.
Solution Approach 2:
The converter module maintains continuous bus activity by pipeline memory requests through the translation process. Instead of idle waiting periods, the system keeps the bus continuously utilized by overlapping translation and memory access operations, ensuring that useful actions (memory accesses) continue without interruption while translations proceed in the background.
3Stability of the object's composition
If the system processes memory requests strictly in order of arrival, then request ordering is maintained, but power consumption increases due to idle bus periods
Solution Approach 1:
The converter module performs preliminary sorting and prioritization of memory requests based on their TLB translation status and urgency. By pre-ordering requests before they reach the bus interface, the system eliminates idle bus periods and ensures continuous operation, thereby reducing power consumption while maintaining logical request ordering through the use of transaction identifiers.
Solution Approach 2:
The system changes the ordering parameter of memory requests from strict arrival order to translation-ready order. The converter module reorders requests based on when their translations will be available, creating an optimized sequence that eliminates bus idle time. This parameter change maintains logical correctness (through transaction ID tracking) while dramatically improving energy efficiency by keeping the bus continuously active.
Data Source
AI summary
A converter module handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.