Memory Access Request Evaluation Circuitry for Timing Penalty Reduction
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Solution Overview
Problem
In modern data processing systems, memory controllers become performance bottlenecks as the number of requesting devices increases, due to their limited ability to optimize access requests across multiple sub-structures within memory devices, leading to inefficiencies and timing penalties.
Innovation Solution
An apparatus and method that includes access request evaluation circuitry to assess incoming requests based on access timing characteristics, allowing only optimal requests to be stored in the pending access requests storage, thereby improving the mix of requests and reducing timing penalties by selectively accepting or rejecting requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller accepts all incoming access requests without evaluation, then the pending access requests storage remains full and the controller appears highly responsive, but the memory device suffers from timing penalties due to poor access request ordering
Solution Approach 1:
The access request evaluation circuitry performs preliminary evaluation of incoming access requests before they are added to the pending access requests storage. This preliminary action assesses whether accepting a request would create suboptimal ordering scenarios that would lead to timing penalties, and prevents such requests from being added to the storage in the first place, rather than dealing with reordering after the fact.
2Loss of time
If the pending access requests storage is made larger to handle more requests, then the memory controller can store more requests for optimization, but the device complexity and cost increase
Solution Approach 1:
The evaluation circuitry changes the parameter of request acceptance from a binary accept/reject decision based solely on storage availability to a decision that also considers the timing characteristics and ordering optimization potential. This parameter change allows the system to maintain a smaller pending storage while achieving better optimization by being more selective about which requests are added.
3Productivity
If the memory controller re-orders access requests in the pending storage to optimize performance, then timing penalties are reduced, but the controller becomes a performance bottleneck with multiple requesting devices
Solution Approach 1:
The evaluation circuitry performs preliminary assessment of access requests before they enter the pending storage, pre-filtering requests that would create timing penalties. This shifts some of the optimization work from the scheduling phase to the admission phase, reducing the burden on the controller's reordering capabilities and allowing it to handle multiple requesting devices more efficiently.
Solution Approach 2:
The access request evaluation circuitry acts as an intermediary between the interface receiving requests and the pending access requests storage. It mediates the admission of requests by evaluating their timing characteristics and making acceptance decisions, thereby protecting the pending storage from receiving requests that would degrade performance and reducing the optimization burden on the main controller.
4Reliability
If the access request evaluation circuitry is added to selectively accept requests, then the mix of requests in pending storage is improved and timing penalties reduced, but the device complexity increases
Solution Approach 1:
The patent replaces complex mechanical reordering mechanisms with an evaluation-based admission control system. Instead of relying solely on sophisticated scheduling algorithms to reorder requests after they enter the pending storage, the system uses evaluation circuitry to pre-assess requests and make admission decisions, substituting a simpler evaluation mechanism for complex post-admission reordering operations.
Data Source
AI summary
An apparatus and method are provided for controlling access to a memory device. The apparatus has a pending access requests storage that is used to store access requests waiting to be issued to the memory device, and memory access control circuitry is then used to issue to the memory device access requests selected from the pending access requests storage. Access requests are received at an interface of the apparatus from at least one requesting device, and access request evaluation circuitry within the apparatus is arranged to apply criteria to determine, for a current access request, whether to accept that current access request or reject that current access request. The criteria applied takes account of at least one access timing characteristic of the memory device. The access request evaluation circuitry is responsive to determining that the current access request is to be accepted, to cause that current access request to be stored in the pending access requests storage. However, if instead the access request is rejected, it is prevented from being added to the pending access requests storage at that time, and instead a rejection indication is issued to the requesting device that issued that current access request. This provides a mechanism for significantly improving the performance of the memory device by providing more selectivity as to what access requests are accepted into the pending access requests storage.