Memory Access Request Reordering for Bandwidth Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory control systems in system-on-chip (SOC) environments face inefficiencies due to insufficient bandwidth and latency issues, particularly when handling multiple memory access requests, as they rely on outdated protocols like ARM's AHB, which struggle with high-bandwidth demands and sequential processing, leading to reduced performance and increased waiting cycles.
Innovation Solution
An apparatus and method that reorders memory access requests to minimize the opening of new rows in memory banks, utilizing a memory access request buffer unit to determine and store request order, a memory access request control unit to distribute requests to banks, and a bank control unit to manage buffer units, allowing for out-of-order processing and efficient bandwidth utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory access requests are processed sequentially using AHB protocol, then system simplicity is maintained, but bandwidth utilization is insufficient and waiting cycles increase
Solution Approach 1:
The memory control apparatus dynamically reorders memory access requests based on bank and row information, transitioning from static sequential processing to dynamic adaptive processing. This allows the system to optimize memory access patterns in real-time, improving bandwidth utilization without requiring a complete protocol overhaul
Solution Approach 2:
The apparatus performs preliminary analysis of memory access requests to identify and group requests targeting the same bank and row before executing them. This pre-processing step enables batched memory operations, reducing the number of row opening operations and improving overall memory bandwidth efficiency
2Productivity
If multiple memory access requests target the same bank and row, then processing efficiency improves through batching, but access latency increases due to sequential handling
Solution Approach 1:
The apparatus maintains continuous memory access operations by overlapping processing of multiple requests. While one request is being executed, the system prepares and queues subsequent requests, ensuring that memory bandwidth is continuously utilized without idle waiting cycles
Solution Approach 2:
The memory access requests are segmented and grouped by bank and row identifiers. Requests targeting the same bank and row are batched together and processed as a group, while requests for different banks can be processed in parallel, reducing overall access latency
3Productivity
If dedicated high-speed memory is added to increase bandwidth, then memory access performance improves, but system cost and complexity increase
Solution Approach 1:
The apparatus changes the operational parameters of the existing memory system by implementing intelligent request reordering and batching mechanisms. This software/firmware-based optimization achieves high bandwidth utilization without requiring hardware upgrades or adding dedicated high-speed memory modules
Data Source
AI summary
Disclosed herein are an apparatus and method for controlling memory. The apparatus includes a memory access request buffer unit, a memory access request control unit, and a bank control unit. The memory access request buffer unit determines and stores memory access request order so that the plurality of memory access requests is processed in the order of input except that memory access requests attempting to access the same bank and the same row are successively processed. The memory access request control unit reads the memory access requests from the memory access request buffer unit in the determined order, distributes the memory access requests to banks, and transfers the memory access requests to memory. The bank control unit stores a preset number of memory access requests in each of buffer units for respective banks, and controls the operating state of each of the banks.