Memory Request Scheduler Using Prioritized Scanners
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Solution Overview
Problem
Existing memory arbiters face a trade-off between memory latency and bandwidth, where focusing on increasing bandwidth can lead to increased latency and vice versa, necessitating a solution that reduces latency while enhancing bandwidth with minimal complexity and die surface area.
Innovation Solution
A system comprising multiple arbiters and a novel time-ordered list scheduler that maintains the relative arrival time of memory requests, using prioritized scanners to select requests based on programmable rules, and counters to manage request prioritization, thereby optimizing the selection process for efficient memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the arbiter focuses on increasing bandwidth by processing efficient requests first, then memory bandwidth increases, but memory latency increases as some requests are bypassed too long
Solution Approach 1:
The scheduler dynamically adjusts request prioritization based on current system state and timing requirements. The arbiter transitions from static bandwidth-optimized scheduling to dynamic scheduling that considers both bandwidth efficiency and latency constraints, adapting the selection criteria in real-time to balance these competing objectives
Solution Approach 2:
The system changes the scheduling parameters by introducing timing-based metrics and latency thresholds into the arbitration decision process. Instead of solely optimizing for bandwidth efficiency, the arbiter now considers multiple parameters including request age, timing requirements, and latency constraints to make balanced scheduling decisions
2Loss of time
If the arbiter focuses on decreasing latency by prioritizing older requests, then memory latency reduces, but memory bandwidth decreases as efficient requests are not processed in optimal sequences
Solution Approach 1:
The scheduling mechanism dynamically balances between latency reduction and bandwidth optimization by adjusting prioritization weights based on system conditions. Rather than statically prioritizing older requests, the arbiter adapts its behavior to consider both timing constraints and efficiency opportunities in real-time
Solution Approach 2:
The system introduces multiple scheduling parameters including efficiency metrics and timing requirements, changing from a single-objective latency minimization approach to a multi-parameter optimization approach that simultaneously considers bandwidth and latency
3Productivity
If a complex arbiter system is designed to balance latency and bandwidth, then performance trade-off improves, but device complexity and die surface area increase
Solution Approach 1:
The arbiter is designed as a multi-functional component that handles both bandwidth optimization and latency management within a single unified structure. This universal design eliminates the need for separate specialized arbiters for each objective, reducing overall system complexity while maintaining performance benefits
Solution Approach 2:
The patent combines multiple scheduling functions (bandwidth optimization, latency management, request prioritization) into a single integrated arbiter unit. By merging these previously separate functions into one cohesive structure, the system achieves balanced performance without proportionally increasing complexity
Data Source
AI summary
A system for selecting memory requests. The system includes arbiters and a time ordered list scheduler. Each arbiter selects a memory request for transmission from at least one client. The scheduler is operable to receive and store memory requests from the arbiters and selects a selected memory request for forwarding to a memory system. The scheduler includes a list structure operable to store memory requests received from the arbiters in a fashion to preserve relative time of arrival of the memory requests. The scheduler includes scanners that are prioritized with respect to one another. Scanners are operable to simultaneously scan contents of the list structure from the oldest to newest requests and determine whether a memory request match is found based on associated programmable rules to locate a memory request candidate. A memory request candidate of a highest priority scanner is selected by the scheduler as the selected memory request.