Memory Request Scheduling with Dynamic Utilization Control

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Solution Overview

Problem

Flash memory storage devices face challenges in optimizing performance and power consumption, often failing to meet performance guarantees due to suboptimal scheduling approaches.

Innovation Solution

A centralized management system is implemented with a storage controller circuit that assigns priorities and costs to requests, using a dynamic utilization counter and weighted round robin algorithm to schedule tasks within a performance envelope, ensuring power and thermal constraints are met.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If flash memory storage devices perform more operations in a given time interval, then productivity is improved, but use of energy increases beyond safe and reliable operation limits

Engineering Contradiction:
Improveoperations per time intervalVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic power management by adjusting the operational state of flash memory channels based on real-time power conditions. The controller transitions channels between active and sleep states, dynamically adapting the number of simultaneously operating channels to match available power headroom, thereby enabling higher productivity when power is abundant while preventing excessive power consumption when resources are limited

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters by modifying the utilization counter that tracks available power headroom. This counter dynamically adjusts the threshold for activating additional channels, allowing the system to scale operations up or down based on real-time power conditions, thus resolving the contradiction between maximizing operations and staying within safe power limits

Inventive Principle:
Principle #35Parameter changes

2Reliability

If existing scheduling approaches are used, then device complexity is reduced, but performance guarantees cannot be met

Engineering Contradiction:
Improveperformance guaranteesVSAvoidscheduling complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the scheduling problem into distinct priority levels (first priority for performance-critical operations, second priority for less critical operations). This segmentation allows the controller to independently manage different request types with different scheduling strategies, ensuring performance guarantees for critical operations while maintaining overall system manageability through structured organization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The utilization counter acts as an intermediary mechanism that mediates between power constraints and scheduling decisions. Rather than directly complex scheduling logic, the counter provides a simplified signal that guides channel activation and request prioritization, thereby meeting performance guarantees through an intermediate control mechanism that avoids excessive scheduling complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If more channels are activated simultaneously, then productivity increases, but power consumption exceeds safe operation limits

Engineering Contradiction:
Improveoperations throughputVSAvoidthermal constraints
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent implements periodic monitoring and adjustment of channel states based on power headroom conditions. The controller periodically evaluates the utilization counter and adjusts channel activation in response to changing power and thermal conditions, enabling high throughput when conditions permit while preventing thermal overload by periodically scaling back operations when limits are approached

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20260044280A1System and Method for Centralized Management of Workload and Parallel Service of Prioritized Requests
Publication Date: 2026.02.12 MICROCHIP TECHNOLOGY INC
  • US20260044280A1 patent drawing
  • US20260044280A1 patent drawing
  • US20260044280A1 patent drawing

AI summary

An apparatus and method for scheduling memory requests including receiving a plurality of requests having a type and associating each request of the received plurality of requests with a corresponding target, which is associated with one channel of a plurality of channels. The method assigning a priority to each request, assigning a utilization cost to each request based on the request's target and request type, and queueing each request of the plurality of requests for scheduling. The method selecting a first request of the received plurality of requests to be scheduled based on its priority, scheduling the first request for processing at a time when the first request utilization cost is less than or equal to a current value of a dynamic utilization counter, and debiting the dynamic utilization counter by the first request utilization cost.