Memory-Request Priority Up-Leveling via VCID Side-Channel Control

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Solution Overview

Problem

Existing memory-request arbitration systems fail to dynamically adjust priority levels in response to changing client requirements, leading to poor quality of service and neglecting memory request dependencies, which can result in suboptimal performance.

Innovation Solution

A memory controller system that allows clients to dynamically adjust priority levels of memory requests within a memory-request buffer via a side channel by asserting an up-level indication corresponding to a virtual channel identification (VCID), thereby increasing priority levels for related memory requests while accounting for dependencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If fixed priority levels are used for memory requests, then arbitration can be performed, but the system cannot adapt when clients' requirements change

Engineering Contradiction:
Improveadaptability to changing client requirementsVSAvoidcomplexity of priority management
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic priority levels that can be adjusted in real-time through a side channel mechanism. Clients can assert up-level indications to increase priority of specific memory requests based on changing requirements, transforming the static arbitration system into an adaptive one without fundamental architectural changes

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the priority parameter of memory requests dynamically. By allowing priority levels to be modified after initial assignment through side channel assertions, the system adapts to varying client needs while maintaining the original arbitration framework

Inventive Principle:
Principle #35Parameter changes

2Productivity

If priority levels are increased for expedited memory requests, then quality of service improves, but memory controller performance may be affected

Engineering Contradiction:
Improvequality of service for memory requestsVSAvoidmemory controller performance
Core Design Contradiction:
ProductivityVSPower

Solution Approach 1:

The patent segments the memory request handling into two independent paths: the main arbitration path and the side channel priority adjustment path. This allows priority modifications to be made without interfering with the core memory controller operations, isolating the QoS improvement mechanism from potential performance impacts

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The side channel acts as an intermediary mechanism between clients and the memory controller's arbitration logic. Priority adjustments are made through this intermediate path, allowing the controller to maintain its original performance characteristics while still responding to priority change requests

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If additional buffer depth is added to handle priority adjustments, then dynamic priority control is enabled, but device complexity increases

Engineering Contradiction:
Improvedynamic priority adjustment capabilityVSAvoidbuffer depth requirements
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The side channel mechanism serves multiple functions: it conveys priority adjustment requests, identifies target memory requests through VCID, and triggers arbitration changes. This multi-functional approach enables dynamic priority control without requiring separate dedicated structures for each function

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system uses existing buffer infrastructure and arbitration logic to handle priority adjustments. Memory requests already in the buffer are identified by VCID and have their priority levels modified in-place, eliminating the need for additional buffer depth or separate storage structures

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250335375A1Memory-Request Priority Up-Leveling
Publication Date: 2025.10.30 GOOGLE LLC
  • US20250335375A1 patent drawing
  • US20250335375A1 patent drawing
  • US20250335375A1 patent drawing

AI summary

The described techniques and apparatuses enable memory-request priority up-leveling. A memory request is received over a virtual channel, VC, and is then added to a memory-request buffer with an original priority-level for the memory request and an indication that the memory request is associated with a virtual channel identification, VCID, of the VC. Related memory requests within the memory-request buffer are also indicated as being associated with the VCID. Responsive to determining that an up-level indication for the VCID is asserted over a side channel, the original priority-levels of the memory request, and other memory-requests in the memory-request buffer having an indication of the VCID, are increased to respective up-leveled priority levels. Responsive to determining that the up-level indication is no longer asserted, the up-leveled priority levels are returned to respective original priority-levels.