Semiconductor Memory Reset via Address Pin Test Mode

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Solution Overview

Problem

Conventional semiconductor memory devices require multiple external pins for reset command application, limiting the number of devices that can be tested simultaneously and increasing test time at the wafer level.

Innovation Solution

A semiconductor memory device design that uses address pins to input a test reset signal, generating an internal test-reset entry signal to drive the reset mode entry, thereby eliminating the need for external pins to apply the reset command, reducing the number of required pins and shortening test time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a reset command is applied through external pins, then the reset mode entry is properly executed, but the number of external input pins increases and test time at wafer level increases

Engineering Contradiction:

Improvereset mode entry executionVSAvoidtest time at wafer level

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The address pins are made multi-functional by enabling them to serve both their original address function and the additional function of inputting reset commands during test mode. This eliminates the need for dedicated external reset pins while ensuring proper reset mode entry execution, thereby reducing the number of external pins required and shortening test time at wafer level

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If multiple external pins are used for reset command application, then the reset function is reliable, but the number of devices that can be tested simultaneously is limited

Engineering Contradiction:

Improvereset functionVSAvoidnumber of devices tested simultaneously

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

By enabling address pins to serve dual purposes (address input and reset command input during test mode), the patent increases the number of devices that can be tested simultaneously. This multi-functionality approach allows test equipment to handle more devices with the same pin resources, thereby improving productivity without compromising reset function reliability

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Ease of operation

If external pins are used for reset command input, then the reset operation is properly controlled, but the device complexity increases

Engineering Contradiction:

Improvereset operation controlVSAvoidnumber of external pins

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

The patent merges the reset command input function with the existing address pin functionality. Instead of adding separate external reset pins, the reset command is combined with address pin signals during test mode. This consolidation reduces the number of external pins required while maintaining proper reset operation control, thereby reducing device complexity

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS7619937B2Semiconductor memory device with reset during a test mode

Publication Date: 2009.11.17 SK HYNIX INC

AI summary

A semiconductor memory device performs a reset operation at a wafer state by using a signal input through an address pin in a test mode. The semiconductor memory device includes a buffer for transferring a reset command in response to a reset-active signal and a test reset signal, a test-reset entry signal generation unit for generating an internal test-reset entry signal in response to the test reset signal, and a rest signal driving unit for driving an active signal of an output signal of the buffer and the internal test-reset entry signal as an internal reset signal for a reset mode entry.