Memory Host Data Reset for Sequential Block Reordering
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Solution Overview
Problem
Data stored in memory systems becomes non-sequential over time due to repeated access operations, leading to increased latency and decreased performance, necessitating a reset operation that erases host data, which is undesirable.
Innovation Solution
A cooperative reset operation between the host system and memory system that reorders data sequentially across pages and blocks without erasing host data, using refresh operations and garbage collection to consolidate data, while maintaining logical block addresses and identifying access frequency and performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a reset operation is performed to reorganize data sequentially, then access latency is reduced and performance is improved, but host data is erased
Solution Approach 1:
The patent segments the memory system into host data areas and non-host data areas, allowing selective reset operations on non-host data while preserving host data. This segmentation enables the system to reorganize sequential data without erasing important host information, thus reducing access latency while preventing data loss.
Solution Approach 2:
The patent performs preliminary actions by identifying and marking host data before the reset operation, then using this information to selectively preserve host data during the reset process. This preliminary identification allows the system to safely reorganize non-host data while maintaining host data integrity.
2Productivity
If data is accessed repeatedly, then data can be retrieved, but data becomes non-sequential leading to increased latency
Solution Approach 1:
The patent implements periodic reset operations that reorganize data sequentially at scheduled intervals or when performance degradation is detected. This periodic action maintains data sequentiality over time, ensuring that repeated access operations do not permanently degrade performance while still allowing necessary data retrieval operations.
Solution Approach 2:
The patent uses feedback mechanisms to monitor data sequentiality and access patterns, then triggers reset operations when performance degradation is detected. This feedback-driven approach allows the system to maintain optimal performance by reorganizing data only when necessary, balancing data access capability with access latency.
3Productivity
If a traditional reset operation is performed, then data is erased and reorganized, but host data integrity is compromised
Solution Approach 1:
The patent segments the memory space into host data regions and non-host data regions, allowing the reset operation to selectively target only non-host data. This segmentation preserves host data integrity while still enabling performance improvement through reorganization of non-host data.
Solution Approach 2:
Instead of erasing all data and reorganizing, the patent inverts the approach by selectively preserving host data and only reorganizing non-host data. This inverted strategy maintains reliability by protecting host data while still achieving performance improvements.
Data Source
AI summary
Methods, systems, and devices for a memory system host data reset function are described. A reset operation may be performed to reset data in a memory system without erasing host data from the memory system. The memory system and a host system may perform the reset operation to sequentially reorder the data across pages and blocks of the memory system, mitigating holes in the data. The reset operation may enable sequentially reordering the data by performing refresh operations on the blocks and performing a subsequent garbage collection operation to consolidate the data within the pages of the refreshed blocks. The host system may reorganize the logical block addresses associated with the blocks and the memory system may perform the refresh operations and the garbage collection operations. The blocks may be refreshed according to an order of access frequency and according to a measure of performance impact on the memory system.