Semiconductor Memory Reset Pad Multi-Function Control

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Solution Overview

Problem

Semiconductor memory apparatuses face limitations in the number of pads available for data storage and operation, as the reset pad remains unused during normal operations, hindering increased data storage and operational capacity.

Innovation Solution

Incorporating a reset pad that can receive and transfer both external reset and control signals, with input buffers and a control unit to activate or deactivate these buffers based on external commands, allowing the pad to be utilized for control operations beyond reset functions, and also enabling the use of additional addresses during non-reset operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of pads is increased to store more data and perform more operations, then data storage capacity and operational capacity are improved, but the physical number of pads available is limited

Engineering Contradiction:
Improvedata storage capacityVSAvoidnumber of pads
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The reset pad is designed to perform multiple functions: it serves as a reset input pad during reset operations and as a control signal input pad during normal operations. This multi-functionality allows the semiconductor memory apparatus to achieve higher data storage capacity and operational capacity without increasing the physical number of pads, directly resolving the contradiction between productivity improvement and limited pad quantity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If the reset pad is dedicated only to reset operations, then reset function reliability is improved, but the pad remains unused during normal operations, reducing overall efficiency

Engineering Contradiction:
Improvereset function reliabilityVSAvoidpad utilization efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The pad's function is made dynamic rather than static. The reset pad can switch between serving as a reset input pad and a control signal input pad based on operational mode. During reset operations, it reliably receives reset signals; during normal operations, it receives control signals. This dynamic functionality maintains reset reliability when needed while significantly improving overall pad utilization efficiency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The reset pad is designed with multi-functionality to handle both reset operations and normal control operations. By making the pad universal, the system ensures reset function reliability when the pad is configured for reset mode while also enabling efficient utilization during normal operations, thereby resolving the contradiction between reliability and productivity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If additional pads are added to handle control signals and addresses, then operational versatility is improved, but the device complexity increases

Engineering Contradiction:
Improveoperational versatilityVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The reset pad is designed to serve multiple purposes: reset input during reset operations and control signal input during normal operations. This multi-functionality enhances operational versatility without requiring additional pads, thereby avoiding the increase in device complexity that would result from adding more pads.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9082470B2Semiconductor memory apparatus and method of operating using the same
Publication Date: 2015.07.14 MIMIRIP LLC
  • US9082470B2 patent drawing
  • US9082470B2 patent drawing
  • US9082470B2 patent drawing

AI summary

A semiconductor memory apparatus includes a reset pad configured to receive and transfer an external reset signal and an external control signal; a first input buffer configured to buffer the external reset signal in response to a buffer control signal and output an internal reset signal; a second input buffer configured to buffer the external control signal in response to the buffer control signal and output an internal control signal; and an input buffer control unit configured to generate the buffer control signal in response to an external command.