Non-volatile Memory Resistance Element Cutout Design
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Solution Overview
Problem
In non-volatile memory devices, the existing manufacturing processes restrict the effective utilization of semiconductor body lines for forming circuit elements, leading to inefficiencies in memory cell size reduction and storage capacity expansion due to non-active areas and increased parasitic capacitance in resistance elements.
Innovation Solution
The implementation of a resistance element design with a first conductive layer, an insulating layer, and a second conductive layer in a stripe pattern, where the second conductive layer includes cutout portions with contact plugs that reduce non-active areas and parasitic capacitance by optimizing the alignment and electrical resistance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional resistance element design is used with full conductive layers, then manufacturing process is simpler, but non-active areas increase and parasitic capacitance increases
Solution Approach 1:
The patent extracts unnecessary portions of the conductive layer to create cutout portions, removing material that would otherwise contribute to parasitic capacitance without serving a functional purpose. This extraction of excess conductive material directly reduces the harmful parasitic capacitance while maintaining the essential resistance element functionality.
Solution Approach 2:
The patent introduces a multi-layer conductive structure with cutout portions that create three-dimensional spatial optimization. By arranging conductive layers at different heights and creating cutouts in specific patterns, the design optimizes electrical characteristics without increasing planar footprint, effectively using vertical dimensionality to reduce parasitic effects.
2Ease of manufacture
If conventional resistance element design is used with full conductive layers, then manufacturing process is simpler, but memory cell area efficiency decreases
Solution Approach 1:
By removing unnecessary conductive material through cutout portions, the patent reduces the effective area occupied by non-functional conductive regions. This extraction of excess material increases the proportion of active area within each memory cell, improving area efficiency without complicating the manufacturing process.
3Productivity
If semiconductor body lines are fully utilized for circuit elements, then manufacturing restrictions are overcome, but manufacturing process complexity increases
Solution Approach 1:
The patent makes the conductive layer structure universal by designing it to serve multiple functions: providing electrical resistance, defining active areas, reducing parasitic capacitance, and enabling area-efficient packing. This multi-functionality allows full utilization of semiconductor body lines without proportionally increasing manufacturing complexity, as the same structural features accomplish multiple objectives.
Data Source
AI summary
A non-volatile memory device comprises a memory area including a memory cell, and a peripheral area including a circuit that drives the memory cell. The circuit includes a first resistance element. The first resistance element includes a first conductive layer extending in a first direction, a first insulating layer provided on the first conductive layer, and a second conductive layer that includes a portion provided on the first insulating layer and an end portion in contact with the first conductive layer.