Memory Resistor Network for Redistribution Layer Impedance Matching
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Solution Overview
Problem
The integration of additional redistribution layers in integrated circuits increases impedance, affecting signal integrity in memory devices like DRAM, which impacts the performance of signal transmission.
Innovation Solution
A memory device incorporating a resistor circuit with multiple resistor sets and fuses that are coupled in parallel to adjust impedance based on the impedance value of the redistribution layer, maintaining signal integrity by equalizing impedance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If redistribution layers are added to change contact locations, then adaptability to various component modules is improved, but impedance increases and signal integrity deteriorates
Solution Approach 1:
A resistor circuit is introduced as an intermediary component between the memory circuit and the redistribution layer. This resistor circuit includes multiple resistor sets that can be selectively coupled in parallel to adjust the overall impedance, serving as a mediator that compensates for the impedance increase caused by the redistribution layer while maintaining signal integrity
Solution Approach 2:
The impedance of the resistor circuit is made adjustable by changing the configuration of resistor sets. Different numbers of resistor sets can be coupled in parallel depending on the impedance value of the redistribution layer, allowing dynamic parameter adjustment to maintain optimal signal integrity while accommodating various component module configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively maintains signal integrity by adjusting impedance to match the impedance of the redistribution layer, thereby improving signal transmission quality in memory devices.
Implementation Method 1
The resistor circuit is coupled to the memory circuit. The resistor circuit includes a first resistor set and a second resistor set. After the first resistor and the second resistor are coupled in parallel and the third resistor and the fourth resistor are coupled in parallel according to an impedance value of the redistribution layer, the first resistor set and the second resistor set are coupled in parallel according to an impedance value of the memory circuit.
Data Source
AI summary
A memory device includes a memory circuit, a redistribution layer and a resistor circuit. The redistribution layer is coupled to the memory circuit. The resistor circuit is coupled to the memory circuit. The resistor circuit includes a first resistor set and a second resistor set. The first resistor set includes a first resistor and a second resistor. The second resistor set includes a third resistor and a fourth resistor. After the first resistor and the second resistor are coupled in parallel and the third resistor and the fourth resistor are coupled in parallel according to an impedance value of the redistribution layer, the first resistor set and the second resistor set are coupled in parallel according to an impedance value of the memory circuit.