Memory Resource Segmentation for Concurrent Single-Level and Multi-Level Programming

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Solution Overview

Problem

Memory systems face delays in single-level operations due to the need to complete multi-level access operations, leading to increased latency and potential processing failures, especially when multi-level operations cannot be delayed until an idle period occurs.

Innovation Solution

Resources in the memory system are grouped to allow continuous single-level and multi-level operations, with one group dedicated to each type, enabling concurrent execution and reducing latency by scheduling folding operations during high utilization periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multi-level access operations are performed to increase storage density, then storage capacity is improved, but access latency increases and single-level operations are delayed

Engineering Contradiction:
Improvestorage capacityVSAvoidaccess latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The memory device is divided into multiple planes, with each plane capable of independent operation. This segmentation allows the system to perform multi-level operations on one plane while simultaneously performing single-level operations on other planes, thereby reducing the latency impact on individual operations while maintaining high storage capacity across all planes.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If multi-level operations are executed to store more data, then storage density is improved, but reliability of timely data access deteriorates

Engineering Contradiction:
Improvestorage densityVSAvoidtimely data access
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

By dividing the memory device into multiple independently operable planes, the system ensures that timely data access requests can be fulfilled on planes not currently engaged in lengthy multi-level operations, thereby maintaining reliability of timely access while achieving high storage density across the entire device.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically selects between single-level and multi-level operations based on the specific data access requirements and current plane availability. This dynamic approach allows the system to optimize for either storage density or access speed depending on the operational context, ensuring reliable timely access when needed while maximizing storage density when appropriate.

Inventive Principle:
Principle #15Dynamics

3Quantity of substance

If all resources are used for multi-level operations, then storage capacity utilization is improved, but productivity of single-level operations decreases

Engineering Contradiction:
Improvecapacity utilizationVSAvoidsingle-level operation throughput
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The memory device is segmented into multiple planes that can operate independently. This allows the system to allocate different planes to different operation types - some planes dedicated to multi-level operations for high capacity utilization, while other planes handle single-level operations for high throughput, thereby resolving the contradiction between capacity utilization and operational productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of using all resources for multi-level operations, the system applies partial action by using only the necessary portion of resources for multi-level operations while leaving other resources available for single-level operations. This partial allocation strategy maintains high capacity utilization for multi-level operations while preserving productivity for single-level operations on available resources.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250013391A1Managing single-level and multi-level programming operations
Publication Date: 2025.01.09 MICRON TECHNOLOGY INC
  • US20250013391A1 patent drawing
  • US20250013391A1 patent drawing
  • US20250013391A1 patent drawing

AI summary

Methods, systems, and devices for managing single-level and multi-level programming operations are described. During a first duration, a first set of resources of a memory system may be configured for single-level operations and a second set of resources of a memory system may be configured to multi-level operations. Also, during the first duration, a first set of data may be received and written to a first virtual block that spans the first set of resources in accordance with a single-level programming operation. Additionally, during the first duration, a second set of data may be transferred from the first set of resources or the second set of resources to a second virtual block that spans the second set of resources in accordance with a multi-level programming operation.