Multi-node Memory Response Indication for Coherence Latency
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Solution Overview
Problem
Multiprocessor computer systems with shared memory architectures face performance drawbacks in cache coherency protocols, including high latency and network congestion due to the need for ordered access rights and acknowledgment messages in directory-based protocols, and bandwidth limitations in broadcast snooping protocols.
Innovation Solution
A multi-node system where response information is maintained in memory, allowing nodes to dynamically switch between broadcast and point-to-point transmission modes based on network conditions, using a hybrid network switch with a mode control unit and mode table to determine the optimal transmission mode for coherence requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If broadcast snooping protocol is used to maintain cache coherency, then all processors can access memory in a totally ordered manner, but network bandwidth is consumed and latency increases due to broadcasting to all processors
Solution Approach 1:
The patent segments the broadcast protocol into two distinct phases: a broadcast phase where coherence requests are sent to all processors to establish ordering, and a point-to-point phase where data is transferred only to the specific requesting processor. This segmentation allows the system to maintain coherency reliability while reducing unnecessary network traffic and improving performance by avoiding redundant data transmissions to processors that do not need the data.
2Productivity
If directory-based protocol is used to reduce network traffic, then bandwidth usage is optimized, but latency increases due to sequential processing of requests and acknowledgment messages
Solution Approach 1:
The patent implements a dynamic transmission mode selection mechanism that adapts between broadcast and point-to-point modes based on system state. The controller determines whether to use broadcast mode (when multiple processors may need the data) or point-to-point mode (when a specific processor requests data), optimizing both bandwidth efficiency and latency by selecting the appropriate mode for each coherence request scenario.
3Reliability
If access rights are modified in the order requests are received to maintain protocol correctness, then coherence protocol behavior is maintained, but processor performance decreases due to out-of-order data availability
Solution Approach 1:
The patent segments the coherence request processing into two independent phases: first, the broadcast phase establishes the total ordering of coherence requests by broadcasting to all processors; second, the point-to-point phase transfers data to the specific requesting processor. This segmentation allows the system to maintain protocol correctness through ordered broadcasting while enabling out-of-order data delivery to individual processors, thereby resolving the contradiction between protocol correctness and processor performance.
Data Source
AI summary
A system may include several nodes coupled by an inter-node network. Each node includes several active devices, a memory subsystem, and an address network and a data network respectively configured to convey address packets and data packets between the active devices and the memory subsystem. The memory subsystem included in one of the nodes is configured to maintain a response indication indicating whether the memory subsystem should send a data packet corresponding to a coherency unit in response to receiving an address packet requesting an access right to the coherency unit from an active device in the same node. The node is also configured to store a node identifier for the coherency unit. The node identifier identifies which of the nodes that has the coherency unit is in a modified global access state.