Semiconductor Memory Error Correction by Data Retention Time
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Solution Overview
Problem
Existing nonvolatile semiconductor memory devices with laminated gate structures face issues with data retention over time, leading to errors and the wasteful use of high-performance error correction mechanisms, which consume power and have large circuit scales, even for short data storage times.
Innovation Solution
A semiconductor memory device with a dual error correction mechanism, using first correcting codes for low power and small circuit scale to correct errors in short-term data and a second correcting code for high-capacity error correction in long-term data, optimizing power consumption and circuit scale based on data retention time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-performance error correction mechanism is used to guarantee correct information restoration after long-term storage, then error correction capability is improved, but power consumption and circuit scale increase
Solution Approach 1:
The patent implements dynamic error correction capability adjustment based on data retention time. The error correction mechanism transitions from a static high-performance design to a dynamic system that adapts its correction strength according to how long data has been stored, using weaker correction for recent data and stronger correction for older data.
Solution Approach 2:
The patent changes the error correction parameters (correction strength, code type) based on the retention time parameter. By monitoring data age and adjusting correction parameters accordingly, the system achieves reliable error correction while minimizing power consumption and circuit complexity for each data item.
2Reliability
If a high-performance error correction mechanism is used to correct errors in short-term stored data, then error correction capability is improved, but power consumption and circuit scale increase
Solution Approach 1:
The patent applies partial error correction action appropriate to the data age. For short-term stored data, only minimal or no error correction is applied since errors are unlikely, rather than applying full-strength correction. This partial action approach eliminates wasted energy on unnecessary correction operations.
3Reliability
If a high-performance error correction mechanism is used for all data regardless of storage time, then error correction capability is improved, but circuit scale increases
Solution Approach 1:
The patent segments the error correction system into multiple levels or modes corresponding to different data retention time ranges. Instead of a single monolithic high-performance correction circuit, the system divides correction functionality into segments that can be selectively activated, reducing overall circuit scale while maintaining necessary correction capability for each segment.
4Reliability
If error correction is applied to all data items uniformly, then error correction capability is improved, but processing time increases
Solution Approach 1:
The patent implements dynamic error correction processing that adapts to data retention time. The processing time and correction intensity are dynamically adjusted based on how long data has been stored, avoiding uniform application of time-consuming correction algorithms to all data items regardless of their actual error risk.
Data Source
AI summary
A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.