Memory Array Retention Voltage Control for Leakage Recovery
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Solution Overview
Problem
Existing solutions for managing retention voltages of digital logic circuits, such as SRAM memory arrays, are inefficient in high leakage conditions, necessitating margins to compensate for manufacturing variations.
Innovation Solution
The system provides granular control over the retention or active state of each digital logic circuit by coupling each circuit to a respective ballast driver and active signal switch, with voltage regulators connected via a bias node, allowing for individual control of memory arrays to transition between active and retention states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If retention voltage is reduced to lower leakage current, then power consumption is reduced, but manufacturing variations cause reliability margins to deteriorate
Solution Approach 1:
The patent divides the memory array into multiple segments or blocks, each with independent retention voltage control. This allows selective application of retention voltage to only those segments that require it, reducing overall leakage current while maintaining reliability for accessed segments. The segmentation enables granular power management without compromising the reliability of active memory regions.
Solution Approach 2:
The patent implements local quality control by applying different retention voltage levels to different regions or blocks of the memory array based on their specific needs. Accessed regions maintain higher voltage for reliability, while non-accessed regions use lower voltage to reduce leakage. This localized approach optimizes the trade-off between power consumption and reliability margins for each specific region.
2Adaptability or versatility
If granular control over retention state is implemented for each digital logic circuit, then power state management precision is improved, but device complexity increases
Solution Approach 1:
The patent employs universal control mechanisms that can manage multiple memory blocks or digital logic circuits using a standardized approach. The retention voltage control circuitry is designed to handle various circuits through a common interface and control logic, reducing the complexity that would otherwise arise from implementing completely separate control systems for each circuit.
Solution Approach 2:
The patent merges the control functions for multiple digital logic circuits into a unified control structure. By combining the retention voltage generation and control logic into shared resources that serve multiple circuits, the patent reduces overall device complexity while maintaining granular control capabilities. The merged control system manages power states across multiple circuits through coordinated operation.
Data Source
AI summary
Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.