Memory Retention Margin Verification for Over-Programming Detection
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Solution Overview
Problem
Current memory systems face challenges in detecting over-programming and erroneous errors in memory cells, which can lead to incorrect data storage and require extensive processing time for error correction, especially when programming multiple cells simultaneously.
Innovation Solution
The method involves using a data retention margin bit count to verify the accuracy of programming by performing extra reads in retention margins after the normal program verify sequence, determining if bits exceed a pre-set threshold, and generating an error if necessary, thereby detecting failure bits and preventing over-programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory cells are programmed in parallel to improve productivity, then programming speed increases, but variations in programming speed occur due to minor structural and operational differences among cells
Solution Approach 1:
The patent applies preliminary action by performing verification operations during the programming process itself, rather than after completion. Multiple verify operations are conducted at different stages of programming to detect and correct threshold voltage variations before they result in erroneous data storage, thereby maintaining programming uniformity while preserving parallel programming speed.
Solution Approach 2:
The patent implements feedback mechanisms through multiple verify operations that continuously monitor the threshold voltage of memory cells during programming. The results of these verification operations are fed back to adjust subsequent programming pulses, ensuring uniform programming across all cells while maintaining high productivity through parallel processing.
2Reliability
If verification operations are performed after programming to ensure reliability, then data storage accuracy improves, but processing time increases
Solution Approach 1:
The patent performs verification operations during the programming process rather than after completion. Multiple verify operations are conducted at different stages to detect and correct errors in real-time, ensuring data storage accuracy while avoiding the time penalty of post-programming verification.
Solution Approach 2:
The patent maintains continuous verification throughout the programming process, integrating verification operations into the programming sequence itself. This continuous approach ensures that reliability is maintained without requiring separate post-programming verification steps that would increase processing time.
3Reliability
If multiple verify operations are performed during programming to detect over-programming, then error detection capability improves, but programming time increases
Solution Approach 1:
The patent performs multiple verify operations during the programming process to detect over-programming errors in real-time. By conducting verification at different stages of programming, the system can identify and correct errors before they result in incorrect data storage, improving reliability without significantly extending the total programming time through efficient integration of verify operations.
Data Source
AI summary
Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence and if the number of bits in these regions is more than a pre-set the memory will fail verify status. A method of verifying data in a memory device includes the steps of: defining an retention margin between adjacent data thresholds; programming the memory device with data; determining whether bits are present in the data retention margin; and if the number of bits in the retention margin exceeds a threshold, generating an error.