Memory Array Retention Voltage Control for Leakage Reduction
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Solution Overview
Problem
Existing solutions for managing retention voltages in digital logic circuits, such as SRAM memory arrays, are inefficient due to high leakage conditions caused by manufacturing variations, leading to over-design and inefficient power management.
Innovation Solution
Implementing a system with granular control over retention and active states of digital logic circuits using a plurality of voltage regulators and ballast drivers, allowing each memory array to be individually managed through active signal switches, enabling efficient current leakage recovery and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If typical solutions for tracking and managing retention voltages are used, then power management is simplified, but leakage current increases due to high leakage conditions and manufacturing variations
Solution Approach 1:
The patent divides the memory array into multiple segments or blocks, each with independent retention voltage control. This allows selective placement of individual memory blocks into retention state based on activity patterns, preventing unnecessary leakage current in inactive blocks while maintaining simplicity through modular control architecture
Solution Approach 2:
The patent implements local retention voltage control where different voltage levels are applied to different memory blocks based on their specific needs. The voltage regulator provides customized retention voltages to individual blocks, optimizing leakage reduction for each block independently while maintaining overall system simplicity
2Loss of energy
If granular control over retention state is implemented for each digital circuit, then leakage current is reduced, but device complexity increases due to multiple voltage regulators and control circuits
Solution Approach 1:
The patent merges multiple retention voltage control functions into a single integrated voltage regulator that can serve multiple memory blocks. The regulator combines global retention voltage generation with local distribution control, reducing overall circuit complexity while maintaining granular control capability for power dissipation optimization
Solution Approach 2:
The voltage regulator is designed with multi-functionality to handle both active and retention states across multiple memory blocks using unified control logic. The same regulator circuit provides retention voltage to different blocks at different times, eliminating the need for separate dedicated circuits for each block and reducing overall device complexity
3Loss of energy
If voltage is reduced to place memory arrays in retention state, then leakage current decreases, but memory access speed decreases
Solution Approach 1:
The patent implements dynamic retention voltage control that adjusts voltage levels based on memory access patterns. The system dynamically transitions memory blocks between retention and active states, applying reduced voltage only when blocks are inactive and full voltage when access is needed, thereby reducing leakage current without compromising access speed
Solution Approach 2:
The patent uses preliminary action by predicting memory access patterns and pre-loading required data blocks from retention state into active state before they are needed. This allows memory blocks to remain in low-power retention state longer, reducing leakage current, while ensuring data availability when needed maintains access speed performance
Data Source
AI summary
Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.