Memory Retry Buffer for Unsuccessful Write Recovery

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Solution Overview

Problem

Memory devices with technologies like CBRAM, RRAM, and MRAM experience cell-to-cell and write-to-write variations in write times, leading to unsuccessful writes, which can result in data loss unless a verify operation is performed and retry mechanisms are implemented.

Innovation Solution

The implementation of a memory system with a controller and a memory device that includes a retry buffer and retry control mechanisms. When a write fails, the information is stored in the retry buffer, and the retry control alerts the controller when the buffer is full, allowing for scheduled retry operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If write operations are performed in memory devices with variable write times, then data storage capacity is improved, but write reliability deteriorates due to unsuccessful writes

Engineering Contradiction:
Improvedata storage capacityVSAvoidwrite reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent implements a verify operation immediately after each write operation to detect unsuccessful writes before they result in data loss. This preliminary verification allows the system to identify and retry failed writes, thereby maintaining high write reliability while preserving data storage capacity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a retry buffer as an intermediary component that temporarily stores information about unsuccessful writes. This buffer acts as a mediator between the write operation and the final data storage, allowing failed writes to be captured, managed, and retried without losing the original data.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If retry mechanisms are implemented to handle unsuccessful writes, then write reliability is improved, but device complexity increases due to additional buffer and control mechanisms

Engineering Contradiction:
Improvewrite reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the retry management function into separate modular components: a retry buffer for storing failed write information, a verify operation for detecting failures, and a retry control mechanism for coordinating retries. This segmentation allows each component to be independently optimized and managed, reducing overall system complexity while maintaining high reliability.

Inventive Principle:
Principle #1Segmentation

3Reliability

If verify operations are performed after every write, then write reliability is improved, but processing time increases due to additional verification steps

Engineering Contradiction:
Improvewrite reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements a self-service retry mechanism where the memory device automatically detects unsuccessful writes through verify operations and initiates retries without requiring external intervention. This self-service approach minimizes processing time by eliminating manual retry coordination while maintaining high write reliability through automatic verification and recovery.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12204469B2Unsuccessful write retry buffer
Publication Date: 2025.01.21 RAMBUS INC
  • US12204469B2 patent drawing
  • US12204469B2 patent drawing
  • US12204469B2 patent drawing

AI summary

A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.