Memory Controller Read Retry Ordering for Defect-Based Error Correction

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Solution Overview

Problem

Existing memory systems face inefficiencies in read retry operations due to fixed retry orders, leading to increased latency and time consumption when dealing with read errors caused by various defects in memory devices.

Innovation Solution

A memory controller performs read retry operations based on a read retry table that sorts defects by occurrence possibility, selecting the most likely defect type for retry, thereby optimizing the retry process and reducing error correction time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a fixed retry order approach is used for read retry operations, then the operation process is simple, but the latency and time consumption for error correction increase

Engineering Contradiction:
Improveread retry operation processVSAvoidlatency and time consumption for error correction
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent applies dynamics by changing the read retry operation from a fixed static order to a dynamic adaptive order. The controller dynamically adjusts the retry sequence based on real-time defect occurrence statistics and characteristics of the storage region, allowing the system to adapt to different error patterns and minimize correction time for each specific case

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of retry order from a fixed constant to a variable parameter that is adjusted based on defect occurrence statistics. By modifying the retry sequence parameter according to observed error patterns in different storage regions, the system optimizes error correction efficiency while maintaining operational simplicity

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If a fixed retry order approach is used for read retry operations, then the system complexity is low, but the error correction efficiency decreases

Engineering Contradiction:
Improvesystem complexityVSAvoiderror correction efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing defect occurrence statistics for different storage regions before actual read operations. The controller maintains a lookup table with pre-analyzed error patterns, allowing it to quickly determine the optimal retry order without complex real-time analysis, thus improving efficiency while keeping system complexity manageable

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system performs self-service by automatically analyzing its own error patterns and adjusting its retry strategy based on observed defect occurrences. The controller monitors read errors, updates defect statistics, and autonomously optimizes the retry order without requiring external intervention or complex external control mechanisms

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11086720B2Memory system and operating method thereof
Publication Date: 2021.08.10 SK HYNIX INC
  • US11086720B2 patent drawing
  • US11086720B2 patent drawing
  • US11086720B2 patent drawing

AI summary

A memory system may include: a memory device including a plurality of storage regions; and a controller. The controller may be coupled between a host and the memory device, and perform a read retry operation when a read error occurs in any one of the storage regions based on occurrence possibilities for a plurality of different type of defects in any one storage region where a read error occurred.