3D Memory Device Revision Circuit for ROM Error Correction
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Solution Overview
Problem
Current memory devices face challenges in correcting output data errors in read-only-memory (ROM) systems, particularly in three-dimensional structures where modifying independent signals is difficult after formation, leading to reliability issues.
Innovation Solution
A memory device with a revision circuit formed on top of the memory cell array, capable of storing and outputting modified ROM data in response to a select signal, and a selection circuit that outputs either the independent signal or modified ROM data based on a ROM control signal, ensuring data correction and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a three-dimensional memory structure is used to increase data storage capacity, then integration is improved, but the ability to modify independent signals after formation deteriorates
Solution Approach 1:
The patent segments the ROM signal path into multiple independent circuits, each capable of being individually tested and revised. This allows specific faulty circuits to be identified and corrected without affecting the entire ROM system, enabling post-formation modification of independent signals while maintaining the three-dimensional structure's high storage capacity.
Solution Approach 2:
The patent introduces dynamic revisability to the ROM system by implementing test operations that can detect errors in independent circuits and apply corrections during operation. This transforms the traditionally static ROM into a dynamically adjustable system where signals can be modified after formation based on detected errors, resolving the contradiction between fixed three-dimensional structure and post-formation adaptability.
2Device complexity
If independent circuits are formed under the memory cell array, then integration is improved, but error correction capability deteriorates
Solution Approach 1:
The patent implements preliminary testing and error detection mechanisms that operate during manufacturing and initial operation. By detecting errors in independent circuits early through test operations and applying corrections before the device enters full service, the system maintains high integration while ensuring reliability through proactive error correction rather than reactive measures.
Solution Approach 2:
The patent establishes feedback loops where test operations continuously monitor independent circuits for errors and trigger correction mechanisms when faults are detected. This feedback system enables the highly integrated three-dimensional structure to maintain reliability by automatically detecting and correcting errors in independent circuits, transforming the static integrated structure into a self-correcting system.
3Reliability
If ROM data is made immutable after formation, then reliability is improved, but adaptability deteriorates
Solution Approach 1:
The patent introduces conditional dynamics to the ROM system by implementing test operations that can detect errors and trigger data modification only when necessary. During normal operation, ROM data remains immutable ensuring reliability, but when test operations detect errors in independent circuits, the system dynamically enables correction mechanisms to modify the affected data, thus achieving both data integrity and necessary adaptability.
Solution Approach 2:
The patent applies local quality changes by allowing ROM data modification only in specific locations where errors are detected through test operations, rather than allowing global modification. This targeted approach maintains the immutability and reliability of unaffected ROM data while enabling correction of specific faulty circuits, resolving the contradiction between overall data integrity and localized adaptability.
Data Source
AI summary
The memory device includes: an independent circuit configured to output an independent signal; a memory cell array formed on a top of the independent circuit, the memory cell array including a plurality of memory cells in which data is stored; a revision circuit formed on a top of the memory cell array, the revision circuit storing modified ROM data different from the independent signal, the revision circuit outputting a ROM control signal and the modified ROM data in response to a select signal when an error occurs in the independent signal in a test operation of the independent circuit formed under the memory cell array; and a selection circuit configured to output the independent signal or the modified ROM data in response to the ROM control signal.