Memory Ring Oscillator Circuit for PVT-Stable Timing

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Solution Overview

Problem

On-chip ring-oscillators (ROs) in memory devices face challenges due to frequency control tolerance and variations in process corners, voltage biases, and temperature, leading to instability and timing errors, especially in applications requiring precise timing.

Innovation Solution

A circuit configuration using transistors connected in a loop, biased by a current source proportional to their threshold voltage, generates oscillating signals that are insensitive to process, voltage, and temperature variations, replacing off-chip crystal oscillators and on-chip phase-locked loops.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If off-chip crystal oscillators and on-chip phase-locked loops are used for frequency control, then frequency accuracy can be maintained, but device complexity and area increase

Engineering Contradiction:
Improvefrequency accuracyVSAvoidcomplexity of frequency control circuit
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts the frequency control function from complex off-chip crystal oscillators and on-chip phase-locked loops, implementing it instead through a simplified ring oscillator circuit with specific transistor configurations that inherently provide PVT compensation, thereby reducing device complexity while maintaining frequency accuracy

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent creates a simplified copy of the frequency control function using ring oscillator circuits that replicate the essential oscillation behavior without requiring the complex supporting infrastructure of crystal oscillators or phase-locked loops, achieving comparable frequency accuracy with reduced complexity

Inventive Principle:
Principle #26Copying

2Area of stationary object

If traditional ring-oscillators are used in memory devices, then area efficiency improves, but timing precision deteriorates due to PVT variations

Engineering Contradiction:
Improvearea efficiencyVSAvoidtiming precision
Core Design Contradiction:
Area of stationary objectVSMeasurement precision

Solution Approach 1:

The patent changes the operating parameters of the ring oscillator by biasing transistors at specific current levels and configuring transistor ratios to compensate for PVT variations, thereby maintaining timing precision while preserving the area efficiency benefits of on-chip oscillation

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements self-compensating mechanisms within the ring oscillator circuit where transistor configurations automatically adjust for PVT variations without requiring external calibration or control circuits, maintaining timing precision through self-service compensation

Inventive Principle:
Principle #25Self-service

3Stability of the object's composition

If frequency control circuits are made more complex to achieve PVT independence, then stability improves, but power consumption increases

Engineering Contradiction:
Improvefrequency stabilityVSAvoidpower consumption
Core Design Contradiction:
Stability of the object's compositionVSUse of energy by moving object

Solution Approach 1:

The patent implements self-compensating mechanisms within the ring oscillator circuit where transistor configurations automatically adjust for PVT variations without requiring external calibration or control circuits, maintaining timing precision through self-service compensation

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20260039280A1Memory devices with reduced timing variation and methods for operating the same
Publication Date: 2026.02.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20260039280A1 patent drawing
  • US20260039280A1 patent drawing
  • US20260039280A1 patent drawing

AI summary

A circuit includes a current source configured to provide a reference current and a plurality of transistors each configured to receive the reference current from the current source. Each of the plurality of transistors has a same conductive type and includes a first source/drain terminal connected to a gate terminal of a first neighboring one of the transistors, a second source/drain terminal connected to ground, and a gate terminal connected to a source/drain terminal of a second neighboring one of the transistors.