Memory System RMW Command Scheduling
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Solution Overview
Problem
Current memory systems face inefficiencies in operation performance due to high overhead in Read-Modify-Write (RMW) operations, which are typically background operations and can hinder processor performance.
Innovation Solution
The implementation of a memory system that includes a processor to generate RMW commands, a scheduler to reorder and schedule these commands based on target segment addresses, and an RMW unit to execute them, thereby reducing the overhead on the processor and improving overall system performance by utilizing resources more efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If RMW operations are performed in sequential order as generated, then data integrity is maintained, but processor overhead increases and operation performance deteriorates
Solution Approach 1:
The scheduler performs preliminary analysis of RMW command dependencies and reorders commands before execution. By pre-determining the optimal execution sequence based on segment address comparisons, the system prepares the command queue in advance, allowing the processor to execute commands more efficiently without maintaining strict sequential order, thus reducing processor overhead while preserving data integrity.
Solution Approach 2:
The system dynamically reorders RMW commands based on their target segment addresses and dependency relationships. Instead of fixed sequential execution, the scheduler adapts the execution order by comparing segment addresses and identifying independent commands that can be executed in parallel or out-of-order, thereby improving productivity while managing the complexity of maintaining data integrity through dynamic dependency tracking.
2Loss of time
If RMW commands are reordered for parallel execution, then execution time is reduced, but complexity of command scheduling increases
Solution Approach 1:
The memory system is divided into multiple segments, and RMW commands are segmented based on their target segment addresses. The scheduler processes commands segment-by-segment, comparing addresses to identify which commands can be executed in parallel within or across segments. This segmentation approach reduces scheduling complexity by localizing dependency analysis to specific segments rather than requiring global analysis of all commands.
Solution Approach 2:
The scheduler uses segment address parameters as the key criterion for reordering commands. By changing the scheduling parameter from strict sequential order to segment address-based ordering, the system enables parallel execution of commands targeting different segments while maintaining simplicity in the scheduling logic. The parameter change transforms the scheduling problem into a more manageable form based on address comparison.
Data Source
AI summary
A memory system includes a memory device including a plurality of segments; a processor configured to generate a Read-Modify-Write (RMW) command on a target segment address corresponding to a target segment among the plurality of segments; a scheduler configured to receive the RMW command from the processor and schedule the RMW command; and a RMW unit configured to execute the RMW command on the memory device according to control of the scheduler, wherein the scheduler compares, when a plurality of RMW commands received from the processor are pending, target segment addresses of the plurality of RMW commands to re-order the plurality of RMW commands.