Memory System Round-Robin Reads to Reduce Plane Wait Time
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Solution Overview
Problem
Existing memory systems face inefficiencies in data transfer operations due to wait times between read operations, particularly in NAND flash memory systems with multiple planes, leading to increased latency and reduced performance.
Innovation Solution
Implementing a round robin processing scheme that hierarchically monitors and controls data transfer across memory packages, dies, and planes, ensuring that data transfer targets are selected alternately and efficiently, thereby minimizing wait times and optimizing data transfer operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer operations are performed sequentially in existing memory systems, then data transfer can be completed, but wait times between read operations increase latency and reduce performance
Solution Approach 1:
The memory system is segmented into multiple independent data transfer paths, each capable of handling read operations simultaneously. The memory controller divides the data transfer task into multiple parallel operations across different memory planes and channels, eliminating sequential wait times and improving overall throughput.
Solution Approach 2:
The patent implements continuous data transfer operations by overlapping read commands across multiple memory planes. While one plane is transferring data, another plane simultaneously performs read operations, ensuring that the memory controller remains continuously productive without idle wait periods between operations.
2Speed
If multiple read operations are performed in parallel across memory planes, then data transfer speed increases, but coordination complexity and control overhead increase
Solution Approach 1:
The patent merges the control functions for multiple parallel read operations into a unified control logic within the memory controller. By combining plane selection, command issuance, and data reception handling into an integrated control mechanism, the system achieves parallel data transfer without proportionally increasing control complexity.
Solution Approach 2:
The memory controller employs periodic round-robin scheduling to alternately select active memory planes for data transfer. This periodic selection pattern simplifies control logic by using a predictable, repeating sequence rather than complex dynamic arbitration, while still enabling efficient parallel operations across multiple planes.
Data Source
AI summary
According to one embodiment, a system includes: a memory, and a controller, wherein the memory includes a first die including first and second planes and a second die including a third plane, and the controller issues a read command to the first and second dies, if a read time for first data in the first plane has ended, a read time for second data in the second plane has ended after the end of the read time for the first data, and a read time for third data in the third plane has ended after the end of the read time for the second data, receives the first data from the first die, receives the third data from the second die after completion of receiving the first data, and receives the second data from the first die after completion of receiving the third data.