Memory Row Address Routing Across Group Regions
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Solution Overview
Problem
Current memory technologies face inefficiencies in power consumption due to numerous row address transmission paths, which increase current consumption and reduce performance.
Innovation Solution
The memory design includes multiple group regions and a control circuit that decodes active instructions to send row addresses based on active command signals and bank group addresses, reducing row address sending paths by identifying target bits to determine the appropriate group region for address transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If row addresses are transmitted through multiple paths to all group regions, then address coverage is complete, but power consumption increases
Solution Approach 1:
The patent extracts and identifies specific target bits from the bank group address that are identical across all bank groups within a group region. By extracting only these critical address bits and transmitting them selectively, the system avoids sending complete row addresses through all possible paths, thereby reducing power consumption while maintaining complete address coverage through the control circuit's routing logic.
Solution Approach 2:
The patent segments the address transmission system into multiple independent paths, each responsible for specific group regions. The control circuit divides the address transmission task among different paths based on the target bit values, allowing parallel processing and reducing the load on individual transmission paths, which lowers overall power consumption.
2Productivity
If row addresses are sent to all group regions, then address accessibility is ensured, but transmission time increases
Solution Approach 1:
The patent performs preliminary identification of target bits within the bank group address before address transmission begins. The control circuit pre-processes the address to determine which group region should receive the row address based on the target bit values, enabling direct routing without trial-and-error or sequential checking, thus reducing address transmission time.
Solution Approach 2:
The patent implements dynamic address routing where the control circuit adaptively selects the transmission path based on the actual target bit values in the bank group address. This dynamic selection allows the system to activate only the necessary transmission paths for the current operation, reducing the time required compared to static approaches that would activate all paths regardless of need.
Data Source
AI summary
A memory is provided in this application, including multiple group regions, a command decoding circuit, and a control circuit. Each group region includes multiple bank groups, and each bank group corresponds to one bank group address. An active instruction is received by the command decoding circuit, and the active instruction is decoded to obtain an active command signal. The bank group address, a row address, and the active command signal are received by the control circuit, and the row address is sent to one of the group regions based on the active command signal and the bank group address.