Memory Row Address Scrambling to Reduce Coupling
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Solution Overview
Problem
As memory devices with increasing capacity and integration face frequent access to adjacent memory cells, they experience issues such as pass gate effect, disturbance, and coupling, leading to errors in data storage due to the high voltage applied to adjacent word lines.
Innovation Solution
A memory device that includes a memory cell array with word lines arranged sequentially based on row addresses, a row decoder that scrambles specific bits of the row address to select non-adjacent word lines, and an anti-fuse array that programs the selection signal for scrambling, preventing adjacent word line access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high voltage is frequently applied to adjacent word lines to turn on transistors, then memory cells can be accessed, but pass gate effect and coupling occur causing data errors
Solution Approach 1:
The patent applies parameter changes by modifying the row address parameters through scrambling operations. The row decoder scrambles specific bits (e.g., LSB and next LSB) of the row address before decoding, which changes the mapping relationship between input addresses and selected word lines. This parameter transformation ensures that frequently accessed adjacent memory locations map to non-adjacent physical word lines, reducing coupling and pass gate effects while maintaining access speed.
Solution Approach 2:
The patent uses inversion by reversing the natural sequential mapping of row addresses to word lines. Instead of adjacent addresses mapping to adjacent word lines, the scrambling mechanism inverts this relationship so that adjacent addresses map to non-adjacent word lines. This inversion fundamentally changes the access pattern to avoid the harmful effects of adjacent word line activation.
2Quantity of substance
If memory device capacity and integration are increased, then more memory cells are available, but gap between word lines decreases causing more coupling
Solution Approach 1:
The patent addresses the coupling problem caused by increased integration by changing the address-to-wordline mapping parameters. The scrambling operation modifies which word lines are activated for given memory addresses, ensuring that even as devices are scaled and word line gaps decrease, the logical adjacency of memory cells does not correspond to physical adjacency of word lines, thereby minimizing coupling effects.
Solution Approach 2:
The patent applies local quality by making the word line selection non-uniform and position-dependent through scrambling. Different regions of the memory array experience different mapping transformations, so that locally adjacent word lines are not simultaneously activated even when logically adjacent memory cells are accessed. This local differentiation reduces coupling in high-density configurations.
3Reliability
If row address bits are scrambled to select non-adjacent word lines, then pass gate effect is reduced, but decoder complexity increases
Solution Approach 1:
The patent manages decoder complexity by implementing scrambling as a parameter transformation layer before the main decoding logic. The scrambler operates on select bits of the row address (typically 2-3 bits) using simple XOR or multiplexer operations, which adds minimal complexity compared to the full decoder structure. This selective parameter modification approach achieves reliability improvement without substantially increasing overall decoder complexity.
Solution Approach 2:
The patent applies segmentation by separating the address processing into distinct stages: a scrambling stage that modifies specific bits, and a decoding stage that processes the scrambled address. This segmentation allows the complex function to be divided into simpler, more manageable components, reducing the complexity burden on any single part of the decoder while achieving the overall goal of non-adjacent word line selection.
Data Source
AI summary
According to an exemplary embodiment, a memory device may include a memory cell array that includes memory cells connected to word lines arranged in sequential order depending on a sequential change of a row address, a row decoder that, for each row address input to the row decoder, scrambles a first bit of the row address and a second bit of the row address depending on a selection signal, thereby forming a scrambled row address, decodes the scrambled row address, and selects a word line from the word lines based on the scrambled row address, and an anti-fuse array that includes an anti-fuse in which a logical value of the selection signal is programmed. A first word line and a second word line of the word lines may be adjacent to each other, and a difference between a first value of the row address corresponding to the first word line and a second value of the row address corresponding to the second word line may be a value corresponding to the first bit.