Memory Block Row Addressing for SLC and MLC Mode Switching

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Solution Overview

Problem

Existing storage devices face inefficiencies in managing storage space and data retention due to the limitations of volatile and nonvolatile memory devices, particularly in switching between single-level cell (SLC) and multi-level cell (MLC) modes, which affect program operation speed, read operation speed, and memory cell degradation.

Innovation Solution

A storage device with a memory controller that sets program operation modes to SLC or MLC based on row addresses, performing operations on a string group basis in SLC mode and on a word line basis in MLC mode, with the memory controller managing row address allocation and program order to optimize storage efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If program operation mode is set to SLC mode for high speed performance, then program operation speed is improved, but storage capacity per memory cell is reduced

Engineering Contradiction:

Improveprogram operation speedVSAvoidstorage capacity per memory cell

Core Design Contradiction:

SpeedVSQuantity of substance

Solution Approach 1:

The memory device dynamically switches between SLC and MLC operation modes based on the row address being accessed. The mode determination unit selects SLC mode for certain row addresses to achieve high-speed operations and MLC mode for other row addresses to maximize storage capacity, allowing the system to adaptively balance between speed and capacity depending on operational requirements

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

Different regions of the memory block are assigned different operation modes based on their row address characteristics. The memory controller applies SLC mode to specific row address ranges while applying MLC mode to other ranges, creating local optimization where speed is prioritized in certain regions and capacity is prioritized in other regions

Inventive Principle:

Principle #3Local quality

2Quantity of substance

If program operation mode is set to MLC mode for high storage capacity, then storage capacity per memory cell is improved, but program operation speed is reduced

Engineering Contradiction:

Improvestorage capacity per memory cellVSAvoidprogram operation speed

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

The system dynamically adjusts the operation mode based on real-time needs by determining whether to use SLC or MLC mode according to the row address. This dynamic switching allows the memory device to achieve high capacity when needed while maintaining the ability to switch to high-speed SLC mode when performance is critical

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The memory block is functionally divided into different operational zones where MLC mode is applied to row addresses requiring high capacity and SLC mode is applied to row addresses requiring high speed, optimizing both capacity and speed in their respective local regions

Inventive Principle:

Principle #3Local quality

3Productivity

If frequent mode switching between SLC and MLC is performed, then storage efficiency is optimized, but memory cell degradation increases

Engineering Contradiction:

Improvestorage efficiencyVSAvoidmemory cell degradation

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The memory controller incorporates a mode management mechanism that tracks the current operation mode and row address to determine when mode switching is necessary. By using feedback about the row address characteristics and current operational state, the controller optimizes mode switching decisions to improve storage efficiency while minimizing unnecessary switches that would accelerate memory cell degradation

Inventive Principle:

Principle #23Feedback

4Speed

If row address allocation is optimized for SLC mode operations, then program operation speed is improved, but compatibility with MLC mode operations is reduced

Engineering Contradiction:

Improveprogram operation speedVSAvoidmode compatibility

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The memory device is designed with universal row address allocation schemes that work across both SLC and MLC modes. The mode determination unit and address allocator cooperate to ensure that the same row address structure can be interpreted correctly in either mode, allowing the system to maintain compatibility with existing address allocation methods while achieving mode-specific performance optimizations

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250372172A1Storage device and method of operating the storage device

Publication Date: 2025.12.04 SK HYNIX INC

AI summary

Provided herein is a memory device. The memory device includes a memory block, an operation processor, and an address allocator. The memory block includes a plurality of string groups connected to a plurality of word lines. The operation processor is configured to set a program operation mode of the memory block to one of a single-level cell (SLC) mode and a multi-level cell (MLC) mode in response to a command received externally from the memory device. The address allocator is configured to allocate a row address of the memory block differently depending on the program operation mode.