Semiconductor Memory Row Block Segmentation for Column Repair
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Solution Overview
Problem
Semiconductor chips, particularly DRAMs, face increased error possibilities due to reduced sizes during manufacturing, and existing repair methods are inadequate in detecting and addressing defects effectively, leading to potential operational errors.
Innovation Solution
A semiconductor memory device with a memory cell array divided into row blocks and segments, utilizing a row decoder to activate spare word-lines and a column decoder to repair defective bit-lines with spare bit-lines across segments, enhancing flexibility and manufacturing yield during column repair operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are reduced in size through fine processes, then manufacturing density and integration are improved, but the possibility of errors occurring during manufacturing process increases
Solution Approach 1:
The memory block is divided into multiple row blocks, and each row block is further divided into multiple segments. This segmentation allows independent repair operations in different segments, enabling flexible column repair that can address manufacturing defects in specific segments without affecting the entire memory block, thus maintaining reliability while preserving high manufacturing density.
Solution Approach 2:
The patent changes the operational parameters of the repair system by enabling cross-segment spare bit-line usage. When a defective bit-line is detected in one segment, the system can activate spare bit-lines from other segments through control signals, effectively changing the operational state from segment-isolated to cross-segment cooperative repair, thereby reducing error possibilities.
2Ease of manufacture
If conventional repair schemes are used, then manufacturing process is simple, but flexibility of column repair operation is insufficient
Solution Approach 1:
By dividing the memory block into multiple segments with independent spare bit-lines and control mechanisms, the system achieves fine-grained repair flexibility. Each segment can be independently repaired using its own spare bit-lines or borrowed from other segments, providing adaptable column repair operations while maintaining a relatively simple manufacturing process that extends conventional repair architectures.
Solution Approach 2:
The spare bit-lines and control circuits are designed to serve multiple functions: they can repair defective bit-lines within the same segment or be shared across different segments. This multi-functionality increases column repair flexibility without requiring entirely separate repair systems for each segment, thus balancing manufacturing simplicity with repair adaptability.
3Productivity
If segment-based spare bit-line utilization is implemented, then column repair flexibility and manufacturing yield are improved, but device complexity increases
Solution Approach 1:
The memory block is segmented into multiple regions, each with dedicated spare bit-lines and control logic. This segmentation enables independent repair operations in each segment, improving manufacturing yield by allowing localized repairs without affecting the entire memory block. The segmented architecture manages complexity by confining repair operations to specific regions rather than requiring global repair coordination.
Solution Approach 2:
Spare bit-lines are pre-configured in each segment during manufacturing, and defect locations are identified and recorded before final product operation. This preliminary preparation of repair resources and defect mapping allows the system to quickly activate appropriate spare bit-lines when defects occur, improving manufacturing yield while managing complexity through pre-established repair pathways rather than requiring complex real-time decision-making.
Data Source
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AI summary
A semiconductor memory device includes a memory cell array and an address decoder. The memory cell array includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of dynamic memory cells coupled to word-lines and bit-lines, each of the plurality of memory blocks are divided into a plurality of row blocks by row block identity bits of a row address, and each of the of row blocks includes a plurality of sub-array blocks arranged in a first direction. The address decoder changes a physical row address of a memory cell that stores or outputs data based on a column address received with a write command or a read command.