Semiconductor Memory Row Decoder Negative Voltage Control
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Solution Overview
Problem
The reliability of semiconductor memory devices is compromised due to unintended negative voltage swings in control signal lines, leading to junction forward issues in row decoders, which can result in unnecessary current flow and transistor latch-up.
Innovation Solution
A semiconductor memory device is designed with a negative voltage generation circuit and a double well structure in the row decoder, where a negative voltage is selectively supplied to control signal lines during periods of negative swing, preventing junction forward by maintaining a sufficient voltage difference across transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional row decoder design is used, then device complexity is low, but reliability deteriorates due to junction forward issues
Solution Approach 1:
The patent applies double well structure (p-well and n-well) to the row decoder transistors, introducing a vertical dimension for voltage control. This allows independent voltage application to different wells, creating a three-terminal transistor configuration that prevents junction forward while maintaining planar device layout.
Solution Approach 2:
The patent introduces a negative voltage generation circuit as an intermediary component that generates and supplies negative voltage to the control signal lines during negative swing periods. This intermediary circuit acts as a buffer between the power supply and the row decoder, preventing harmful voltage effects without requiring fundamental changes to the decoder logic.
2Reliability
If negative voltage is continuously supplied to control signal lines, then junction forward is prevented, but energy consumption increases
Solution Approach 1:
The patent implements periodic negative voltage supply controlled by a negative swing detection circuit. The negative voltage is generated and applied only during specific periods when negative swing is detected on control signal lines, rather than continuously. This timing-controlled approach maintains reliability while minimizing energy consumption by activating the negative voltage generation only when needed.
3Reliability
If conventional single well structure is used, then manufacturing is simpler, but unnecessary current flow occurs
Solution Approach 1:
The patent transitions from a single well structure to a double well structure (p-well and n-well stacked vertically). This vertical dimensionality change allows independent electrical control of each well through separate terminals, enabling prevention of junction forward current while maintaining compatibility with standard CMOS fabrication processes.
Solution Approach 2:
The patent applies different voltage conditions to different regions (wells) of the transistor structure. The p-well and n-well can have different potential levels independently controlled, allowing localized voltage adjustment to prevent current flow issues in specific regions without affecting the entire device uniformly.
Data Source
AI summary
A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.