Non-Volatile Memory Row Decoder for High-Voltage Word-Line Switching
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges in efficiently implementing row decoders due to the need for FETs that can withstand high supply voltages, leading to complex manufacturing processes and additional electric losses.
Innovation Solution
The proposed solution involves a row decoder design that uses low-power FETs and a power supply circuit to generate auxiliary voltages, allowing the row decoder to support high supply voltages while using the same production technology for all FETs, and includes a discharge circuit with n-channel and p-channel FETs to connect word-lines to ground efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FETs are designed to withstand high supply voltages, then the memory can operate under high supply voltages, but the manufacturing process becomes complex and costs increase
Solution Approach 1:
The row decoder is divided into two separate circuits: a first circuit (demultiplexer) operating at low supply voltage to generate enable signals, and a second circuit (switching circuit with n-channel FET) operating at high supply voltage to connect word-lines to ground. This segmentation allows each circuit to be optimized for its specific voltage requirement, enabling high voltage operation without requiring all FETs to be manufactured with high voltage capability.
2Reliability
If FETs are designed to withstand high supply voltages, then the memory can operate under high supply voltages, but additional electric losses occur
Solution Approach 1:
The row decoder is divided into two separate circuits: a first circuit (demultiplexer) operating at low supply voltage to generate enable signals, and a second circuit (switching circuit with n-channel FET) operating at high supply voltage to connect word-lines to ground. This segmentation allows each circuit to be optimized for its specific voltage requirement, enabling high voltage operation without requiring all FETs to be manufactured with high voltage capability.
3Reliability
If different production technologies are used for high voltage FETs, then high supply voltage operation is enabled, but device complexity and manufacturing costs increase
Solution Approach 1:
The row decoder is divided into two separate circuits: a first circuit (demultiplexer) operating at low supply voltage to generate enable signals, and a second circuit (switching circuit with n-channel FET) operating at high supply voltage to connect word-lines to ground. This segmentation allows each circuit to be optimized for its specific voltage requirement, enabling high voltage operation without requiring all FETs to be manufactured with high voltage capability.
Solution Approach 2:
The n-channel FET acts as an intermediary switching element that is controlled by enable signals from the low-voltage demultiplexer. This intermediary approach allows the high-voltage word-line connection to be controlled without requiring the controlling FETs in the demultiplexer to also withstand high voltages, thus simplifying the overall device complexity.
Data Source
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Figure 2A~3
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AI summary
A non-volatile memory (20) comprising a row decoder (202a) is described. The row decoder (202a) comprises for each of a plurality of word-line (WL) a respective pull-up (30) connected to a first supply voltage (VHV) and a switching circuit (32) for selectively connecting one of the word-lines (WL) to ground. Moreover, the row decoder (202a) comprises a demultiplexer (2020a) configured to assert an enable signal (EN) as a function of an address signal (ADR), wherein the demultiplexer (2020a) is supplied by a second supply voltage (VLV) being smaller than the first supply voltage (VHV). Specifically, the switching circuit (32) comprises two n-channel FETs (MN2, MN3) connected in series between the word-line (WL) and ground, wherein the gate terminal of the first n-channel FET (MN2) is connected to a first signal (EN1) and the gate terminal of the second n-channel FET (MN3) is connected to a second voltage (V2). A bias circuit (300) is configured to set the voltage between the two n-channel FETs (MN2, MN3) to the second voltage (V2) when the two n-channel FETs (MN2, MN3) are opened. Moreover, the switching circuit (32) comprises a p-channel FET (MP1) connected between the word-line (WL) and the second voltage (V2), wherein the gate terminal of the p-channel FET (MP1) is connected to a second signal (EN2). The row decoder comprises also for each word-line (WL) a first delay circuit (34, 36) and a second delay circuit (38, 40) configured to generate the first signal (EN1) and the second signal (EN2), respectively, as a function of the enable signal (EN).