Semiconductor Memory Row Decoder Transfer Gate Segmentation
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Solution Overview
Problem
The large circuit area of NAND flash memory devices due to the use of large-size MOSFETs in row decoders for transferring high voltages to word lines increases the manufacturing cost and reduces yield, necessitating a reduction in circuit scale and process complexity.
Innovation Solution
The implementation of a semiconductor memory device with a row decoder that uses transfer gates to divide word lines into groups, allowing common use of transfer gates across memory cell arrays, reducing the number of decoding circuits and interconnections, and employing a layout that simplifies the connection of transfer gates to word lines, thereby minimizing circuit area and preventing short circuits during scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If large-size MOSFETs are used in row decoders to transfer high voltages to word lines, then voltage transfer capability is improved, but circuit area increases
Solution Approach 1:
The patent divides the row decoder into multiple segments, each handling a subset of word lines. Transfer gates are distributed across different blocks rather than concentrated in one large decoder, reducing the area of any single decoder unit while maintaining overall voltage transfer capability across all word lines.
Solution Approach 2:
The patent utilizes three-dimensional stacking of memory cell arrays and distributes row decoders across different vertical layers and horizontal blocks. This spatial distribution in multiple dimensions reduces the planar circuit area required for row decoders while preserving voltage transfer functionality through strategically placed transfer gates.
2Manufacturing precision
If row decoders are arranged on both sides of memory cell array, then voltage distribution is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the memory device into multiple blocks with distributed row decoders on both sides of each block. Each block operates semi-independently with its own transfer gates, simplifying the manufacturing process by allowing modular fabrication and reducing inter-block interference while maintaining uniform voltage distribution across the entire array.
Solution Approach 2:
The patent implements row decoders on both sides of each block (excessive action) but only activates the necessary decoders for each specific operation. This partial activation approach ensures uniform voltage distribution when needed while simplifying manufacturing by using standardized block structures that can be selectively enabled.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the circuit area of the row decoders and the overall memory device, enhances manufacturing efficiency, and prevents short circuits caused by scaling, while maintaining operational integrity by ensuring accurate voltage control across memory cell arrays.
Implementation Method 1
a row decoder including transfer gates that respectively transfer voltages to the word lines
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a first memory cell array including a first block that includes memory cells, a second memory cell array including a second block that includes memory cells, word lines arranged in the first and second memory cell arrays, and a row decoder including transfer gates that respectively transfer voltages to the word lines. Word lines arranged in the first block include first and second groups, word lines arranged in the second block include third and fourth groups, and the first and third groups commonly use the transfer gates.