Memory Row Decoder Virtual Bank Activation for Calculation Speed
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Solution Overview
Problem
The communication speed between the central processing unit (CPU) and random access memory (RAM) acts as a bottleneck due to slower data access compared to the CPU's calculation speed, prompting the need for improved memory devices that can perform calculations closer to the memory to reduce this bottleneck.
Innovation Solution
The memory device supports two operation modes: a first mode where a single bank is activated for normal access and a second mode where multiple banks are activated as a virtual bank to enhance calculation speed, allowing for embedded calculation functions and improved bandwidth utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple banks are activated simultaneously as a virtual bank, then calculation speed and bandwidth utilization are improved, but device complexity and control difficulty increase
Solution Approach 1:
The memory device is divided into multiple banks, each capable of independent activation. The row decoder block segments the address decoding process to selectively activate specific banks or multiple banks simultaneously as a virtual bank, enabling parallel operations while maintaining manageable control through structured segmentation.
Solution Approach 2:
The memory device dynamically switches between different operation modes (single bank activation vs. multiple banks as virtual bank) based on access patterns. The row decoder block adapts its behavior to activate either one bank or multiple banks simultaneously, providing dynamic control that optimizes performance for different computational workloads without requiring permanent complex circuitry.
2Speed
If multiple banks are activated as a virtual bank, then data access speed is improved, but the complexity of address decoding increases
Solution Approach 1:
The row decoder block is designed with multi-functionality to handle both single bank activation and multiple bank activation as a virtual bank using the same basic decoding structure. This universal approach allows the decoder to achieve faster data access through virtual bank activation without requiring entirely separate decoding circuits, thereby limiting the increase in address decoding complexity.
3Productivity
If embedded calculation functions are added to memory, then communication bottleneck is reduced, but device complexity increases
Solution Approach 1:
The patent merges calculation functions with the memory device by utilizing the row decoder block and bank activation mechanisms to perform calculations within the memory structure itself. Multiple banks are combined into a virtual bank that can be activated simultaneously, enabling embedded calculations that reduce the need for external CPU intervention and thereby reduce communication bottleneck without requiring entirely separate calculation hardware.
Data Source
AI summary
A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.