Semiconductor Memory Device Row Decoder Voltage Segmentation
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Solution Overview
Problem
In NAND flash memory devices, increased integration leads to parasitic capacitance between memory cells, causing data stored in unselected memory cells to be altered during data input and output operations due to voltage transfer and electron discharge.
Innovation Solution
A semiconductor memory device design that includes a memory cell array with selected and unselected memory blocks, where a voltage generator outputs operating voltages to global lines and a row decoder transfers these voltages to local lines of selected blocks while supplying a ground voltage to local lines of unselected blocks, preventing electron discharge and data alteration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high integration is implemented to increase data storage capacity, then storage capacity is improved, but parasitic capacitance between memory cells increases causing data retention to deteriorate
Solution Approach 1:
The memory block is divided into a selected memory block and unselected memory blocks. The row decoder selectively applies voltages only to the selected memory block while applying ground voltage to unselected memory blocks, thereby segmenting the voltage application and preventing parasitic capacitance interference between memory blocks.
Solution Approach 2:
Different voltage conditions are applied to different regions: the selected memory block receives operating voltages (Vread, Vpass1, Vpass2) necessary for data operations, while unselected memory blocks receive ground voltage to maintain low potential. This local differentiation prevents charge leakage in unselected blocks while enabling operations in the selected block.
2Ease of operation
If high voltage is applied to a memory cell during data operations, then data input and output operations are enabled, but voltage is transferred to adjacent memory cells through capacitor coupling causing electron discharge
Solution Approach 1:
Before data operations are performed on the selected memory block, the row decoder preemptively applies ground voltage to the unselected memory blocks. This preliminary action creates a protective potential difference that prevents voltage transfer through parasitic capacitance during subsequent high-voltage operations on the selected block.
Solution Approach 2:
The row decoder acts as an intermediary device that controls voltage distribution between selected and unselected memory blocks. It mediates the voltage application process by using switching elements to connect unselected memory blocks to ground potential, thereby isolating them from the high-voltage operations performed on the selected block.
3Productivity
If voltage is applied to unselected memory blocks during data operations, then data operations can be performed on selected blocks, but electrons stored in floating gates of unselected memory cells are discharged altering stored data
Solution Approach 1:
The harmful effect of voltage application on unselected memory blocks is extracted and eliminated by connecting these blocks to ground potential through the row decoder. This removes the source of electron discharge from floating gates in unselected blocks while preserving the ability to perform operations on the selected block.
Solution Approach 2:
The row decoder performs preliminary voltage setup by applying ground voltage to unselected memory blocks before data operations begin. This preliminary grounding prevents electron discharge during subsequent operations, ensuring data integrity in unselected blocks while enabling efficient operations on the selected block.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances data retention characteristics by preventing data changes in unselected memory blocks during I/O operations, maintaining accurate data storage and retrieval.
Implementation Method 1
the intervals between the memory cells are narrowed, which leads to increased parasitic capacitance between the memory cells. Then, when a high voltage is applied to a memory cell, the high voltage is also transferred to the adjacent memory cells because of the capacitor coupling phenomenon
Data Source
AI summary
A semiconductor memory device includes a memory cell array configured to include a plurality of memory blocks, a voltage generator configured to output operating voltages for data input and output to global lines, and a row decoder configured to transfer the operating voltages to local lines of a memory block, selected from among the plurality of memory blocks, and supply a ground voltage to local lines of unselected memory blocks in response to address signals.