Memory Row Hammering Prevention via Dynamic Register Allocation
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Solution Overview
Problem
Memory devices experience data loss due to row hammering, where intense activation of a specific row causes voltage stress on adjacent rows, leading to data errors, and existing solutions fail to effectively prevent this phenomenon.
Innovation Solution
A memory device with control logic that includes registers and counters to record and manage row addresses, activation counts, and lifetime counts, evicting row addresses with low activation and no lifetime count to prevent data loss by performing refresh operations on adjacent rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If row addresses are recorded in all registers, then data loss prevention coverage is improved, but device complexity increases due to more counters and management logic
Solution Approach 1:
The patent changes the parameter of register management by introducing a selection unit that dynamically chooses which register to allocate based on activation counts. Instead of uniformly managing all registers, the system prioritizes registers with lower activation counts, thereby preventing row hammering while managing complexity through intelligent parameter selection rather than brute-force monitoring of all registers equally.
2Measurement precision
If activation count and lifetime count are tracked for all row addresses, then row hammering detection accuracy is improved, but loss of time increases due to additional counting operations
Solution Approach 1:
The patent applies preliminary action by pre-allocating registers to row addresses before row hammering occurs. The selection unit proactively identifies and assigns registers based on current activation counts, preparing the system in advance to detect and respond to potential row hammering threats. This preliminary registration reduces the need for continuous real-time analysis during active operations, thereby reducing time loss.
3Reliability
If registers are allocated to frequently activated rows, then row hammering prevention is improved, but productivity decreases due to register allocation overhead
Solution Approach 1:
The patent implements dynamics by making the register allocation flexible and adaptive rather than static. The selection unit continuously monitors activation counts and dynamically reassigns registers as patterns change. This dynamic approach allows the system to adapt to varying access patterns without permanent overhead, maintaining productivity while improving row hammering prevention through responsive register management.
Data Source
AI summary
Disclosed is a memory device which includes a memory core that includes a plurality of memory cells, and control logic that receives a first active command and a first row address from an external device and activates memory cells corresponding to the first row address from among the plurality of memory cells in response to the first active command. The control logic includes registers and counters. The control logic records the first row address in one of the registers, counts an activation count of the first row address by using a first counter of the counters, and counts a lifetime count of the first row address by using a second counter of the counters.