Memory Sub-Array Row Mapping for Word Line Interference Errors
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Solution Overview
Problem
Data errors in memory cells of semiconductor storage devices due to interference between adjacent word lines are difficult to correct with existing Error Correction Codes (ECC) when the number of errors exceeds the correction limit.
Innovation Solution
Implementing a semiconductor storage device with sub arrays where logical row addresses corresponding to physical rows differ between sub arrays, using multiplexers to selectively drive word lines and disperse error bits across different logical row addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is read from or written into a memory cell array, then data access is enabled, but memory cells connected to word lines adjacent to a selected word line are disturbed due to interference between adjacent word lines
Solution Approach 1:
The memory cell array is divided into multiple sub-arrays, and the word lines are segmented such that adjacent word lines in different sub-arrays are offset. When a read/write operation is performed on a selected word line in one sub-array, the adjacent word lines in other sub-arrays do not contain data, thereby eliminating the interference disturbance while maintaining fast data access.
2Reliability
If data correction with ECC is performed, then error correction is attempted, but data correction becomes difficult when many memory cells have errors due to disturbance
Solution Approach 1:
By segmenting the memory into sub-arrays with offset word line arrangements, the invention prevents widespread errors from occurring simultaneously across many memory cells. This segmentation approach reduces the number of errors that ECC needs to handle, making error correction more feasible and reducing the complexity of the correction process.
Solution Approach 2:
The invention converts the potential harm of adjacent word line interference into a benefit by deliberately arranging that adjacent word lines in different sub-arrays are offset. This arrangement ensures that when one word line is active, its adjacent lines in other sub-arrays are inactive, transforming the interference problem into a solution that reduces error rates and simplifies ECC correction.
Data Source
AI summary
A memory includes a cell array including first and second sub arrays including memory cells and simultaneously driven in a read or a write operation. First lines are connected to the cells corresponding to one of physical rows, where the physical row is the cells arranged in a first direction in the cell array. Second lines are connected to the cells arranged in a second direction intersecting with the first direction in the cell array. A decoder selects a selection line from among the first lines in accordance with a logical row address corresponding to each of the physical rows and applies a read voltage or a write voltage to the selection line. A sense amplifier detects data from the second lines. Logical row addresses corresponding to physical rows adjacent to a certain physical row among the physical rows differ between the first sub array and the second sub array.