Memory Controller Row Recovery Using ECC and CRC Parities
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Solution Overview
Problem
Current memory controllers are inadequate in addressing row and bank faults, particularly due to process shrinkage, and fail to effectively correct multiple-bit errors in semiconductor memory devices, limiting data reliability.
Innovation Solution
A memory controller with a fault determination circuit using ECC and CRC parities to identify faulty rows and a recovery circuit that repairs faults using data from other rows and repair parities, ensuring data reliability by correcting errors and maintaining system integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error detection/correction logic (SECDED) is used, then 1-bit error correction is achieved, but multiple-bit errors and row/bank faults cannot be effectively corrected
Solution Approach 1:
The memory rows are divided into multiple segments (first row, second row, third row, etc.) within a repair unit. Each segment can be independently detected and repaired. The parity information is also segmented into first parity, second parity, and third parity, each corresponding to different row segments, enabling granular error detection and correction across multiple bits and rows
Solution Approach 2:
The patent extends error correction from a single-dimension (1-bit per row) to multi-dimensional by implementing correction across multiple rows and multiple parity types. The repair unit concept creates a two-dimensional correction space (rows × parity types) that can handle multiple-bit errors and row/bank faults that conventional single-dimension SECDED cannot address
2Productivity
If process shrinkage continues to increase capacity and speed, then memory performance improves, but chip kill and reliability reduction occur
Solution Approach 1:
The system performs preliminary error detection using first and second parities before data access, and maintains ready-to-use third parity information for immediate repair. When a faulty row is detected, the recovery circuit can instantly retrieve data from other rows in the repair unit using the pre-established parity relationships, preventing chip kill before it occurs
Solution Approach 2:
The patent establishes repair units with multiple rows and corresponding parities in advance, creating a cushion against potential failures. When process shrinkage causes defects, the pre-configured redundancy and parity information provide a buffer that allows error correction and prevents catastrophic failure
Data Source
AI summary
A memory controller including: a fault determination circuit to receive first parity, second parity, and data read out from a first row of a memory device, and determine, based on a result of a first error detection operation using the first parity and a result of a second error detection operation using the second parity, whether the first row is faulty; a parity storage circuit to store a repair parity for repairing a fault of a row of a plurality of rows of the memory device, wherein the plurality of rows constitutes a repair unit, and wherein the repair unit includes the first row and one or more second rows; and a recovery circuit to repair a fault of the first row by using data of at least one of the second rows and the repair parity, when the first row is determined to be a faulty row.