Memory Controller Row Recovery Using ECC, CRC, and Repair Parity
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Solution Overview
Problem
Current memory controllers are inadequate in addressing multi-bit errors and row faults in semiconductor memory devices, particularly due to limitations in error detection and correction capabilities, which can lead to reduced data reliability and chip failures.
Innovation Solution
A memory system with a fault determination circuit using both ECC and CRC parities to detect faulty rows and a recovery circuit that repairs data using repair parities from other rows, ensuring accurate fault detection and correction across multiple rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC logic is used for error detection and correction, then single-bit errors can be corrected, but multi-bit errors and row faults cannot be effectively addressed
Solution Approach 1:
The memory system is divided into multiple repair units, each containing a plurality of memory rows and associated repair parity information. This segmentation allows independent error correction for each repair unit, enabling the system to handle multi-bit errors and row faults that span across traditional ECC boundaries by treating each repair unit as an independent correction domain.
Solution Approach 2:
The patent introduces a new dimension of error correction by organizing memory into repair units with repair parity information that operates at a different hierarchical level than traditional row-level ECC. This dimensional change allows the system to detect and correct errors that affect entire rows or multiple rows simultaneously, extending beyond the capabilities of conventional single-row ECC logic.
2Reliability
If process shrinkage is reduced to maintain reliability, then manufacturing cost increases, but if process shrinkage is continued, then chip kill and row faults increase
Solution Approach 1:
The system performs preliminary error detection using parity information before errors propagate and cause chip kill. By detecting errors at the repair unit level and correcting them using repair parity, the system prevents minor process variations from escalating into catastrophic failures, thereby maintaining reliability without requiring more conservative (and costly) manufacturing processes.
Solution Approach 2:
The patent implements a feedback mechanism where error detection results trigger automatic correction operations using stored repair parity information. This closed-loop feedback system continuously monitors and corrects errors caused by process shrinkage, allowing the system to maintain high reliability despite manufacturing challenges associated with advanced process nodes.
3Reliability
If repair parity is stored for each repair unit, then fault recovery capability is enhanced, but memory capacity is reduced
Solution Approach 1:
The patent optimizes the parameters of repair units by carefully selecting the number of rows per repair unit and the corresponding repair parity size. This parameter optimization achieves an efficient balance where sufficient repair capacity is provided to handle expected error rates while minimizing the overhead penalty on usable memory capacity. The repair unit structure allows flexible configuration to match specific application requirements.
Solution Approach 2:
Instead of applying uniform error correction across the entire memory array, the patent applies repair parity locally to specific repair units. This local quality approach concentrates correction resources where they are most needed (in units that are prone to row faults) while leaving other areas with lower error rates to use full capacity, thereby optimizing the overall balance between reliability and capacity.
Data Source
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AI summary
A memory controller (100) including: a fault determination circuit (110) to receive first parity (PAR_ECC), second parity (PAR_CRC), and data (DATA) read out from a first row of a memory device (200), and determine, based on a result of a first error detection operation (111) using the first parity (PAR_ECC) and a result of a second error detection operation (112) using the second parity (PAR_CRC), whether the first row is faulty; a parity storage circuit (140) to store a repair parity (PAR_Rep) for repairing a fault of a row of a plurality of rows of the memory device (200), wherein the plurality of rows constitutes a repair unit (210), and wherein the repair unit (210) includes the first row and one or more second rows; and a recovery circuit (120) to repair a fault of the first row by using data of at least one of the second rows and the repair parity (PAR_Rep), when the first row is determined to be a faulty row.