Memory Row Redundancy Repair Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory row architectures experience reduced electrical performance and efficiency due to signal differences among normal memory sections caused by the placement of redundancy memory sections, which affect the ability to repair failed memory units effectively.
Innovation Solution
Implementing a redundancy memory section on one side of each normal memory section, ensuring even distribution and coupling of redundancy sections to maintain uniform signal levels across all normal memory sections, forming distinct redundancy repair modules to address failed units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy memory sections are added to replace failed memory units in conventional memory row architecture, then the repair capability for failed memory units is improved, but the signal levels of normal memory sections become non-uniform due to the placement of redundancy sections, resulting in degraded electrical performance and efficiency
Solution Approach 1:
The memory row architecture is segmented into multiple independent memory sections, each with its own locally coupled redundancy memory section. This segmentation isolates the signal characteristics of each section, preventing signal level non-uniformity from affecting the entire memory row. Each segment maintains uniform signal levels independently while providing repair capability for its associated normal memory sections.
Solution Approach 2:
The redundancy memory sections are locally coupled to specific normal memory sections rather than being globally distributed. This local quality approach ensures that each normal memory section interacts with its own redundancy section, maintaining consistent signal levels within each local group. The local coupling preserves electrical performance by preventing signal level variations that would occur with global redistribution.
2Adaptability or versatility
If redundancy memory sections are distributed throughout the memory row architecture, then the ability to repair failed memory units is enhanced, but the electrical performance and efficiency of the whole memory row architecture deteriorates due to signal differences
Solution Approach 1:
The memory row is divided into multiple segments, each containing normal memory sections and their associated redundancy memory sections. This segmentation allows each segment to operate independently with uniform signal levels, maintaining electrical efficiency while providing distributed repair flexibility across the entire memory row architecture.
Solution Approach 2:
Within each segmented memory row, the normal memory sections and their locally coupled redundancy memory sections maintain equipotential signal levels. This equipotentiality within segments ensures uniform electrical performance while the overall segmented architecture provides the adaptability needed for flexible repair operations across different memory sections.
Data Source
AI summary
The present invention discloses a memory row architecture having memory row redundancy repair function. The memory row architecture includes a plurality of normal memory sections and a plurality of redundancy memory sections, wherein a number of the plurality of normal memory sections is more than two, a number of the plurality of redundancy memory sections is equal to the number of the plurality of normal memory sections, and a redundancy memory section is implemented in one side of each of the plurality of normal memory sections. In addition, the plurality of normal memory sections and the plurality of redundancy memory sections respectively having an odd serial number make up a first memory row redundancy repair module, and the plurality of normal memory sections and the plurality of redundancy memory sections respectively having an even serial number make up a second memory row redundancy repair module.